From patchwork Sat Jun 1 18:30:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 10971463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 79B981575 for ; Sat, 1 Jun 2019 18:36:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 682CE28C3E for ; Sat, 1 Jun 2019 18:36:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59C6128C69; Sat, 1 Jun 2019 18:36:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E1B3128C3E for ; Sat, 1 Jun 2019 18:36:25 +0000 (UTC) Received: from localhost ([127.0.0.1]:40008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hX8rh-0006aV-4j for patchwork-qemu-devel@patchwork.kernel.org; Sat, 01 Jun 2019 14:36:25 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hX8nV-0002sq-Kh for qemu-devel@nongnu.org; Sat, 01 Jun 2019 14:32:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hX8nS-0005ui-Ha for qemu-devel@nongnu.org; Sat, 01 Jun 2019 14:32:03 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59860 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hX8nS-0005Q1-5R for qemu-devel@nongnu.org; Sat, 01 Jun 2019 14:32:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D63071A1E2A; Sat, 1 Jun 2019 20:30:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A8CC91A1DC0; Sat, 1 Jun 2019 20:30:55 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sat, 1 Jun 2019 20:30:44 +0200 Message-Id: <1559413846-4402-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559413846-4402-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1559413846-4402-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 6/8] target/mips: Clean up dsp_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Aleksandar Markovic Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/dsp_helper.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/target/mips/dsp_helper.c b/target/mips/dsp_helper.c index 739b69d..8c58eeb 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/dsp_helper.c @@ -22,8 +22,10 @@ #include "exec/helper-proto.h" #include "qemu/bitops.h" -/* As the byte ordering doesn't matter, i.e. all columns are treated - identically, these unions can be used directly. */ +/* + * As the byte ordering doesn't matter, i.e. all columns are treated + * identically, these unions can be used directly. + */ typedef union { uint8_t ub[4]; int8_t sb[4]; @@ -1445,9 +1447,15 @@ target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt) return temp; } -#define PRECR_QH_PW(name, var) \ -target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \ - uint32_t sa) \ + +/* + * In case sa == 0, use rt2, rt0, rs2, rs0. + * In case sa != 0, use rt3, rt1, rs3, rs1. + */ +#define PRECR_QH_PW(name, var) \ +target_ulong helper_precr_##name##_qh_pw(target_ulong rs, \ + target_ulong rt, \ + uint32_t sa) \ { \ uint16_t rs3, rs2, rs1, rs0; \ uint16_t rt3, rt2, rt1, rt0; \ @@ -1456,8 +1464,6 @@ target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \ MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ \ - /* When sa = 0, we use rt2, rt0, rs2, rs0; \ - * when sa != 0, we use rt3, rt1, rs3, rs1. */ \ if (sa == 0) { \ tempD = rt2 << var; \ tempC = rt0 << var; \ @@ -1965,7 +1971,8 @@ SHIFT_PH(shra_r, rnd16_rashift); #undef SHIFT_PH /** DSP Multiply Sub-class insns **/ -/* Return value made up by two 16bits value. +/* + * Return value made up by two 16bits value. * FIXME give the macro a better name. */ #define MUL_RETURN32_16_PH(name, func, \ @@ -3274,11 +3281,15 @@ target_ulong helper_dextr_l(target_ulong ac, target_ulong shift, CPUMIPSState *env) { uint64_t temp[3]; + target_ulong ret; shift = shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); - return (temp[1] << 63) | (temp[0] >> 1); + + ret = (temp[1] << 63) | (temp[0] >> 1); + + return ret; } target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, @@ -3286,6 +3297,7 @@ target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; shift = shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3305,7 +3317,9 @@ target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, set_DSPControl_overflow_flag(1, 23, env); } - return (temp[1] << 63) | (temp[0] >> 1); + ret = (temp[1] << 63) | (temp[0] >> 1); + + return ret; } target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, @@ -3313,6 +3327,7 @@ target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; shift = shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3338,7 +3353,10 @@ target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, } set_DSPControl_overflow_flag(1, 23, env); } - return (temp[1] << 63) | (temp[0] >> 1); + + ret = (temp[1] << 63) | (temp[0] >> 1); + + return ret; } #endif