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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id v8sm87339107pgs.82.2019.08.11.01.07.11 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 11 Aug 2019 01:07:12 -0700 (PDT) From: Bin Meng To: Alistair Francis , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Sun, 11 Aug 2019 01:06:38 -0700 Message-Id: <1565510821-3927-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565510821-3927-1-git-send-email-bmeng.cn@gmail.com> References: <1565510821-3927-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP At present we only allow symmetric harts to be created. In order to support heterogeneous harts like SiFive FU540, update hart array's "cpu-type" property to allow cpu type to be set per hart, separated by delimiter ",". The frist cpu type before the delimiter is assigned to hart 0, and the second cpu type before delimiter is assigned to hart 1, and so on. If the total number of cpu types supplied in "cpu-type" property is less than number of maximum harts, the last cpu type in the property will be used to populate remaining harts. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/riscv_hart.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 3dd1c6a..27093e0 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -58,13 +58,55 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int hart, static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - int n; + char *cpu_types; + char *first_type, *last_type, *tmp_type; + int n = 0; s->harts = g_new0(RISCVCPU, s->num_harts); - for (n = 0; n < s->num_harts; n++) { - riscv_hart_realize(s, n, s->cpu_type, errp); + /* we should not touch the original s->cpu_type */ + cpu_types = g_strdup(s->cpu_type); + + /* + * Expect s->cpu_type property was initialized this way: + * + * "cpu-type-a": symmetric harts + * "cpu-type-a,cpu-type-b,cpu-type-c": heterogeneous harts + * + * For heterogeneous harts, hart cpu types are separated by delimiter ",". + * The frist cpu type before the delimiter is assigned to hart 0, and the + * second cpu type before delimiter is assigned to hart 1, and so on. + * + * If the total number of cpu types is less than s->num_harts, the last + * cpu type in s->cpu_type will be used to populate remaining harts. + */ + + first_type = strtok(cpu_types, ","); + riscv_hart_realize(s, n++, first_type, errp); + tmp_type = strtok(NULL, ","); + if (!tmp_type) { + /* symmetric harts */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, first_type, errp); + } + } else { + /* heterogeneous harts */ + while (tmp_type) { + if (n >= s->num_harts) { + break; + } + riscv_hart_realize(s, n++, tmp_type, errp); + last_type = tmp_type; + tmp_type = strtok(NULL, ","); + } + + /* populate remaining harts using the last cpu type in s->cpu_type */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, last_type, errp); + } } + + g_free(cpu_types); } static void riscv_harts_class_init(ObjectClass *klass, void *data)