| Message ID | 1568183141-67641-3-git-send-email-zhiwei_liu@c-sky.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: support vector extension | expand |
On Wed, Sep 11, 2019 at 2:36 PM liuzhiwei <zhiwei_liu@c-sky.com> wrote: > From: LIU Zhiwei <zhiwei_liu@c-sky.com> > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.c | 6 +++++- > target/riscv/cpu.h | 2 ++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd..9f93ce7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -109,7 +109,7 @@ static void set_resetvec(CPURISCVState *env, int > resetvec) > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVV); > set_priv_version(env, PRIV_VERSION_1_11_0); > set_resetvec(env, DEFAULT_RSTVEC); > } > @@ -406,6 +406,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error > **errp) > if (cpu->cfg.ext_u) { > target_misa |= RVU; > } > + if (cpu->cfg.ext_v) { > + target_misa |= RVV; > + } > > set_misa(env, RVXLEN | target_misa); > } > @@ -441,6 +444,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, true), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c992b1d..2c7072a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -67,6 +67,7 @@ > #define RVC RV('C') > #define RVS RV('S') > #define RVU RV('U') > +#define RVV RV('V') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > @@ -250,6 +251,7 @@ typedef struct RISCVCPU { > bool ext_c; > bool ext_s; > bool ext_u; > + bool ext_v; > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > -- > 2.7.4 > > > Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8d07bd..9f93ce7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,7 +109,7 @@ static void set_resetvec(CPURISCVState *env, int resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVV); set_priv_version(env, PRIV_VERSION_1_11_0); set_resetvec(env, DEFAULT_RSTVEC); } @@ -406,6 +406,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_u) { target_misa |= RVU; } + if (cpu->cfg.ext_v) { + target_misa |= RVV; + } set_misa(env, RVXLEN | target_misa); } @@ -441,6 +444,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c992b1d..2c7072a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVV RV('V') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -250,6 +251,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_v; bool ext_counters; bool ext_ifencei; bool ext_icsr;