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[Resend,2/3] i386: Add macro for stibp

Message ID 1571729728-23284-3-git-send-email-cathy.zhang@intel.com (mailing list archive)
State New, archived
Headers show
Series Add CPU model for intel processor Cooper Lake | expand

Commit Message

Zhang, Cathy Oct. 22, 2019, 7:35 a.m. UTC 
stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955

Add a macro for it to allow CPU models to report it when host supports.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.h | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e757149..8f8efd7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -717,6 +717,8 @@  typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
+/* Single Thread Indirect Branch Predictors */
+#define CPUID_7_0_EDX_STIBP     (1U << 27)
 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/
 #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)  /*Core Capability*/
 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */