From patchwork Thu Jan 23 11:38:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 11347687 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B5BF1398 for ; Thu, 23 Jan 2020 12:53:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10C0E22522 for ; Thu, 23 Jan 2020 12:53:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="OpyedlyL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10C0E22522 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:56578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iubz9-0002BR-Fq for patchwork-qemu-devel@patchwork.kernel.org; Thu, 23 Jan 2020 07:53:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36493) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iuatp-0008Sh-DF for qemu-devel@nongnu.org; Thu, 23 Jan 2020 06:43:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iuatn-0005FS-I3 for qemu-devel@nongnu.org; Thu, 23 Jan 2020 06:43:49 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:25936 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iuatn-0005Dg-86 for qemu-devel@nongnu.org; Thu, 23 Jan 2020 06:43:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1579779825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m/K/XDCafeDf0g4CDZc1YBwsFcS5JjP8MB6Y+dlLONY=; b=OpyedlyLx1tYY9viQyHYz9Hv7RACa0akGARm0m72DG5HxekfBBPidONJPUWAXCUVPompXQ AWdfJLjxebNZ7+sSojPOdMaHkerP8QnuSCCVzyxM0wZA46ZgmkG9iOZYSgX2/fuaCNc4DS q0Fen19OfmmiUW2mwKWYUz7vFPbp2sg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-268-3I2hC9hLP5uNIGJ-khL8nQ-1; Thu, 23 Jan 2020 06:43:41 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BCB96DB60; Thu, 23 Jan 2020 11:43:40 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id E54D01001B2C; Thu, 23 Jan 2020 11:43:39 +0000 (UTC) From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH REPOST v3 71/80] sparc/sun4m: use memdev for RAM Date: Thu, 23 Jan 2020 12:38:36 +0100 Message-Id: <1579779525-20065-72-git-send-email-imammedo@redhat.com> In-Reply-To: <1579779525-20065-1-git-send-email-imammedo@redhat.com> References: <1579779525-20065-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: 3I2hC9hLP5uNIGJ-khL8nQ-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" memory_region_allocate_system_memory() API is going away, so replace it with memdev allocated MemoryRegion. The later is initialized by generic code, so board only needs to opt in to memdev scheme by providing MachineClass::default_ram_id and using MachineState::ram instead of manually initializing RAM memory region. Patch moves ram size check into sun4m_hw_init() and drops ram_init() moving remainder to sun4m_hw_init() as well, as it was the only place that called it. Also it rewrites impl. of RamDevice a little bit, which could serve as an example of frontend device for RAM backend. (Caveats are: 1. it doesn't check for memdev backend being mapped since it's been usurped by generic machine to handle majority of machines which don't have RAM frontend device 2. it still lacks 'addr' property and still has hardcoded sysbus_mmio_map() in board init. If done right, board should set 'addr' property and bus/machine plug handler should map it during device realize time. ) Further improvements were left as exercise for the future, since frontends are out scope of RAM conversion to memdev. Signed-off-by: Igor Mammedov Acked-by: Mark Cave-Ayland --- CC: mark.cave-ayland@ilande.co.uk CC: atar4qemu@gmail.com --- hw/sparc/sun4m.c | 73 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 2aaa5bf..834ad2a 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -777,63 +777,42 @@ static const TypeInfo prom_info = { typedef struct RamDevice { SysBusDevice parent_obj; - - MemoryRegion ram; - uint64_t size; + HostMemoryBackend *memdev; } RamDevice; /* System RAM */ static void ram_realize(DeviceState *dev, Error **errp) { RamDevice *d = SUN4M_RAM(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); - memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", - d->size); - sysbus_init_mmio(sbd, &d->ram); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); } -static void ram_init(hwaddr addr, ram_addr_t RAM_size, - uint64_t max_mem) +static void ram_initfn(Object *obj) { - DeviceState *dev; - SysBusDevice *s; - RamDevice *d; - - /* allocate RAM */ - if ((uint64_t)RAM_size > max_mem) { - error_report("Too much memory for this machine: %" PRId64 "," - " maximum %" PRId64, - RAM_size / MiB, max_mem / MiB); - exit(1); - } - dev = qdev_create(NULL, "memory"); - s = SYS_BUS_DEVICE(dev); - - d = SUN4M_RAM(dev); - d->size = RAM_size; - qdev_init_nofail(dev); - - sysbus_mmio_map(s, 0, addr); + RamDevice *d = SUN4M_RAM(obj); + object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, + (Object **)&d->memdev, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG, &error_abort); + object_property_set_description(obj, "memdev", "Set RAM backend" + "Valid value is ID of a hostmem backend", + &error_abort); } -static Property ram_properties[] = { - DEFINE_PROP_UINT64("size", RamDevice, size, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void ram_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ram_realize; - dc->props = ram_properties; } static const TypeInfo ram_info = { .name = TYPE_SUN4M_MEMORY, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(RamDevice), + .instance_init = ram_initfn, .class_init = ram_class_init, }; @@ -880,6 +859,13 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, unsigned int smp_cpus = machine->smp.cpus; unsigned int max_cpus = machine->smp.max_cpus; + if (machine->ram_size > hwdef->max_mem) { + error_report("Too much memory for this machine: %" PRId64 "," + " maximum %" PRId64, + machine->ram_size / MiB, hwdef->max_mem / MiB); + exit(1); + } + /* init CPUs */ for(i = 0; i < smp_cpus; i++) { cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); @@ -888,9 +874,13 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, for (i = smp_cpus; i < MAX_CPUS; i++) cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); + /* Create and map RAM frontend */ + dev = qdev_create(NULL, "memory"); + object_property_set_link(OBJECT(dev), OBJECT(machine->ram_memdev), + "memdev", &error_fatal); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); - /* set up devices */ - ram_init(0, machine->ram_size, hwdef->max_mem); /* models without ECC don't trap when missing ram is accessed */ if (!hwdef->ecc_base) { empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); @@ -1078,7 +1068,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); - fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); @@ -1415,6 +1405,7 @@ static void ss5_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss5_type = { @@ -1434,6 +1425,7 @@ static void ss10_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss10_type = { @@ -1453,6 +1445,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss600mp_type = { @@ -1472,6 +1465,7 @@ static void ss20_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss20_type = { @@ -1490,6 +1484,7 @@ static void voyager_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo voyager_type = { @@ -1508,6 +1503,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss_lx_type = { @@ -1526,6 +1522,7 @@ static void ss4_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss4_type = { @@ -1544,6 +1541,7 @@ static void scls_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo scls_type = { @@ -1562,6 +1560,7 @@ static void sbook_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo sbook_type = {