| Message ID | 1580428993-4767-8-git-send-email-aleksandar.markovic@rt-rk.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/avr merger | expand |
On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.markovic@rt-rk.com> wrote: > From: Michael Rolnik <mrolnik@gmail.com> > > Add helpers for instructions that need to interact with QEMU. Also, > add stubs for unimplemented instructions. Instructions SPM and WDR > are left unimplemented because they require emulation of complex > peripherals. The implementation of instruction SLEEP is very limited > due to the lack of peripherals to generate wake interrupts. Memory > access instructions are implemented here because some address ranges > actually refer to CPU registers. > > Signed-off-by: Michael Rolnik <mrolnik@gmail.com> > Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> > --- Hello, Michael. Regarding this and patches 8-14, I did not find any functional inaccuracies. "avrtiny" issues (lack of support for cores with fewer registers) are agreed to be addressed later on, some time after the merge, as not critical for the rest of series. I had, and still have some concerns about missing comments and code readibility in general (details can be seen in my previuos reviews). I have some concerns about lack of usage of enum AVRFeature in some functions (instead of int). I have some concerns abuot functions organization too. But, all of these concerns are not related to the final functionality. In my view, it is even too risky to address them at this stage of the series. They can be easily addressed after the series merge. Therefore: For patches 7-14: Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> > target/avr/helper.c | 203 ++++++++++++++++++++++++++++++ > ++++++++++++++++++++++ > target/avr/helper.h | 29 ++++++++ > 2 files changed, 232 insertions(+) > create mode 100644 target/avr/helper.h > > diff --git a/target/avr/helper.c b/target/avr/helper.c > index 354def2..c582312 100644 > --- a/target/avr/helper.c > +++ b/target/avr/helper.c > @@ -137,3 +137,206 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, > int size, > > return true; > } > + > +/* > + * helpers > + */ > + > +void helper_sleep(CPUAVRState *env) > +{ > + CPUState *cs = env_cpu(env); > + > + cs->exception_index = EXCP_HLT; > + cpu_loop_exit(cs); > +} > + > +void helper_unsupported(CPUAVRState *env) > +{ > + CPUState *cs = env_cpu(env); > + > + /* > + * I count not find what happens on the real platform, so > + * it's EXCP_DEBUG for meanwhile > + */ > + cs->exception_index = EXCP_DEBUG; > + if (qemu_loglevel_mask(LOG_UNIMP)) { > + qemu_log("UNSUPPORTED\n"); > + cpu_dump_state(cs, stderr, 0); > + } > + cpu_loop_exit(cs); > +} > + > +void helper_debug(CPUAVRState *env) > +{ > + CPUState *cs = env_cpu(env); > + > + cs->exception_index = EXCP_DEBUG; > + cpu_loop_exit(cs); > +} > + > +void helper_break(CPUAVRState *env) > +{ > + CPUState *cs = env_cpu(env); > + > + cs->exception_index = EXCP_DEBUG; > + cpu_loop_exit(cs); > +} > + > +void helper_wdr(CPUAVRState *env) > +{ > + CPUState *cs = env_cpu(env); > + > + /* WD is not implemented yet, placeholder */ > + cs->exception_index = EXCP_DEBUG; > + cpu_loop_exit(cs); > +} > + > +/* > + * This function implements IN instruction > + * > + * It does the following > + * a. if an IO register belongs to CPU, its value is read and returned > + * b. otherwise io address is translated to mem address and physical > memory > + * is read. > + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI > implementation > + * > + */ > +target_ulong helper_inb(CPUAVRState *env, uint32_t port) > +{ > + target_ulong data = 0; > + > + switch (port) { > + case 0x38: /* RAMPD */ > + data = 0xff & (env->rampD >> 16); > + break; > + case 0x39: /* RAMPX */ > + data = 0xff & (env->rampX >> 16); > + break; > + case 0x3a: /* RAMPY */ > + data = 0xff & (env->rampY >> 16); > + break; > + case 0x3b: /* RAMPZ */ > + data = 0xff & (env->rampZ >> 16); > + break; > + case 0x3c: /* EIND */ > + data = 0xff & (env->eind >> 16); > + break; > + case 0x3d: /* SPL */ > + data = env->sp & 0x00ff; > + break; > + case 0x3e: /* SPH */ > + data = env->sp >> 8; > + break; > + case 0x3f: /* SREG */ > + data = cpu_get_sreg(env); > + break; > + default: > + /* not a special register, pass to normal memory access */ > + cpu_physical_memory_read(OFFSET_IO_REGISTERS + port, &data, 1); > + } > + > + return data; > +} > + > +/* > + * This function implements OUT instruction > + * > + * It does the following > + * a. if an IO register belongs to CPU, its value is written into the > register > + * b. otherwise io address is translated to mem address and physical > memory > + * is written. > + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI > implementation > + * > + */ > +void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) > +{ > + data &= 0x000000ff; > + > + switch (port) { > + case 0x38: /* RAMPD */ > + if (avr_feature(env, AVR_FEATURE_RAMPD)) { > + env->rampD = (data & 0xff) << 16; > + } > + break; > + case 0x39: /* RAMPX */ > + if (avr_feature(env, AVR_FEATURE_RAMPX)) { > + env->rampX = (data & 0xff) << 16; > + } > + break; > + case 0x3a: /* RAMPY */ > + if (avr_feature(env, AVR_FEATURE_RAMPY)) { > + env->rampY = (data & 0xff) << 16; > + } > + break; > + case 0x3b: /* RAMPZ */ > + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { > + env->rampZ = (data & 0xff) << 16; > + } > + break; > + case 0x3c: /* EIDN */ > + env->eind = (data & 0xff) << 16; > + break; > + case 0x3d: /* SPL */ > + env->sp = (env->sp & 0xff00) | (data); > + break; > + case 0x3e: /* SPH */ > + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { > + env->sp = (env->sp & 0x00ff) | (data << 8); > + } > + break; > + case 0x3f: /* SREG */ > + cpu_set_sreg(env, data); > + break; > + default: > + /* not a special register, pass to normal memory access */ > + cpu_physical_memory_write(OFFSET_IO_REGISTERS + port, &data, 1); > + } > +} > + > +/* > + * this function implements LD instruction when there is a posibility to > read > + * from a CPU register > + */ > +target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) > +{ > + uint8_t data; > + > + env->fullacc = false; > + > + if (addr < NUMBER_OF_CPU_REGISTERS) { > + /* CPU registers */ > + data = env->r[addr]; > + } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { > + /* IO registers */ > + data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); > + } else { > + /* memory */ > + cpu_physical_memory_read(OFFSET_DATA + addr, &data, 1); > + } > + return data; > +} > + > +/* > + * this function implements ST instruction when there is a posibility to > write > + * into a CPU register > + */ > +void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) > +{ > + env->fullacc = false; > + > + /* Following logic assumes this: */ > + assert(OFFSET_CPU_REGISTERS == OFFSET_DATA); > + assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + > + NUMBER_OF_CPU_REGISTERS); > + > + if (addr < NUMBER_OF_CPU_REGISTERS) { > + /* CPU registers */ > + env->r[addr] = data; > + } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { > + /* IO registers */ > + helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); > + } else { > + /* memory */ > + cpu_physical_memory_write(OFFSET_DATA + addr, &data, 1); > + } > +} > diff --git a/target/avr/helper.h b/target/avr/helper.h > new file mode 100644 > index 0000000..bf08750 > --- /dev/null > +++ b/target/avr/helper.h > @@ -0,0 +1,29 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > + */ > + > +DEF_HELPER_1(wdr, void, env) > +DEF_HELPER_1(debug, void, env) > +DEF_HELPER_1(break, void, env) > +DEF_HELPER_1(sleep, void, env) > +DEF_HELPER_1(unsupported, void, env) > +DEF_HELPER_3(outb, void, env, i32, i32) > +DEF_HELPER_2(inb, tl, env, i32) > +DEF_HELPER_3(fullwr, void, env, i32, i32) > +DEF_HELPER_2(fullrd, tl, env, i32) > -- > 2.7.4 > >
diff --git a/target/avr/helper.c b/target/avr/helper.c index 354def2..c582312 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -137,3 +137,206 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } + +/* + * helpers + */ + +void helper_sleep(CPUAVRState *env) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); +} + +void helper_unsupported(CPUAVRState *env) +{ + CPUState *cs = env_cpu(env); + + /* + * I count not find what happens on the real platform, so + * it's EXCP_DEBUG for meanwhile + */ + cs->exception_index = EXCP_DEBUG; + if (qemu_loglevel_mask(LOG_UNIMP)) { + qemu_log("UNSUPPORTED\n"); + cpu_dump_state(cs, stderr, 0); + } + cpu_loop_exit(cs); +} + +void helper_debug(CPUAVRState *env) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); +} + +void helper_break(CPUAVRState *env) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); +} + +void helper_wdr(CPUAVRState *env) +{ + CPUState *cs = env_cpu(env); + + /* WD is not implemented yet, placeholder */ + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); +} + +/* + * This function implements IN instruction + * + * It does the following + * a. if an IO register belongs to CPU, its value is read and returned + * b. otherwise io address is translated to mem address and physical memory + * is read. + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation + * + */ +target_ulong helper_inb(CPUAVRState *env, uint32_t port) +{ + target_ulong data = 0; + + switch (port) { + case 0x38: /* RAMPD */ + data = 0xff & (env->rampD >> 16); + break; + case 0x39: /* RAMPX */ + data = 0xff & (env->rampX >> 16); + break; + case 0x3a: /* RAMPY */ + data = 0xff & (env->rampY >> 16); + break; + case 0x3b: /* RAMPZ */ + data = 0xff & (env->rampZ >> 16); + break; + case 0x3c: /* EIND */ + data = 0xff & (env->eind >> 16); + break; + case 0x3d: /* SPL */ + data = env->sp & 0x00ff; + break; + case 0x3e: /* SPH */ + data = env->sp >> 8; + break; + case 0x3f: /* SREG */ + data = cpu_get_sreg(env); + break; + default: + /* not a special register, pass to normal memory access */ + cpu_physical_memory_read(OFFSET_IO_REGISTERS + port, &data, 1); + } + + return data; +} + +/* + * This function implements OUT instruction + * + * It does the following + * a. if an IO register belongs to CPU, its value is written into the register + * b. otherwise io address is translated to mem address and physical memory + * is written. + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation + * + */ +void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) +{ + data &= 0x000000ff; + + switch (port) { + case 0x38: /* RAMPD */ + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD = (data & 0xff) << 16; + } + break; + case 0x39: /* RAMPX */ + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX = (data & 0xff) << 16; + } + break; + case 0x3a: /* RAMPY */ + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY = (data & 0xff) << 16; + } + break; + case 0x3b: /* RAMPZ */ + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ = (data & 0xff) << 16; + } + break; + case 0x3c: /* EIDN */ + env->eind = (data & 0xff) << 16; + break; + case 0x3d: /* SPL */ + env->sp = (env->sp & 0xff00) | (data); + break; + case 0x3e: /* SPH */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp = (env->sp & 0x00ff) | (data << 8); + } + break; + case 0x3f: /* SREG */ + cpu_set_sreg(env, data); + break; + default: + /* not a special register, pass to normal memory access */ + cpu_physical_memory_write(OFFSET_IO_REGISTERS + port, &data, 1); + } +} + +/* + * this function implements LD instruction when there is a posibility to read + * from a CPU register + */ +target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +{ + uint8_t data; + + env->fullacc = false; + + if (addr < NUMBER_OF_CPU_REGISTERS) { + /* CPU registers */ + data = env->r[addr]; + } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { + /* IO registers */ + data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); + } else { + /* memory */ + cpu_physical_memory_read(OFFSET_DATA + addr, &data, 1); + } + return data; +} + +/* + * this function implements ST instruction when there is a posibility to write + * into a CPU register + */ +void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) +{ + env->fullacc = false; + + /* Following logic assumes this: */ + assert(OFFSET_CPU_REGISTERS == OFFSET_DATA); + assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + + NUMBER_OF_CPU_REGISTERS); + + if (addr < NUMBER_OF_CPU_REGISTERS) { + /* CPU registers */ + env->r[addr] = data; + } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { + /* IO registers */ + helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); + } else { + /* memory */ + cpu_physical_memory_write(OFFSET_DATA + addr, &data, 1); + } +} diff --git a/target/avr/helper.h b/target/avr/helper.h new file mode 100644 index 0000000..bf08750 --- /dev/null +++ b/target/avr/helper.h @@ -0,0 +1,29 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ + +DEF_HELPER_1(wdr, void, env) +DEF_HELPER_1(debug, void, env) +DEF_HELPER_1(break, void, env) +DEF_HELPER_1(sleep, void, env) +DEF_HELPER_1(unsupported, void, env) +DEF_HELPER_3(outb, void, env, i32, i32) +DEF_HELPER_2(inb, tl, env, i32) +DEF_HELPER_3(fullwr, void, env, i32, i32) +DEF_HELPER_2(fullrd, tl, env, i32)