@@ -158,7 +158,6 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
static void zynq_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
@@ -168,6 +167,12 @@ static void zynq_init(MachineState *machine)
qemu_irq pic[64];
int n;
+ /* max 2GB ram */
+ if (machine->ram_size > 0x80000000) {
+ error_report("RAM size more than %d is not supported", 0x80000000);
+ exit(EXIT_FAILURE);
+ }
+
cpu = ARM_CPU(object_new(machine->cpu_type));
/* By default A9 CPUs have EL3 enabled. This board does not
@@ -184,14 +189,9 @@ static void zynq_init(MachineState *machine)
&error_fatal);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
- /* max 2GB ram */
- if (ram_size > 0x80000000) {
- ram_size = 0x80000000;
- }
-
/* DDR remapped to address zero. */
memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
- ram_size);
+ machine->ram_size);
memory_region_add_subregion(address_space_mem, 0, ext_ram);
/* 256K of on-chip memory */
@@ -300,7 +300,7 @@ static void zynq_init(MachineState *machine)
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);
- zynq_binfo.ram_size = ram_size;
+ zynq_binfo.ram_size = machine->ram_size;
zynq_binfo.nb_cpus = 1;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;