From patchwork Tue Feb 11 00:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11374393 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 261AD109A for ; Tue, 11 Feb 2020 00:47:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F153C20733 for ; Tue, 11 Feb 2020 00:47:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="y717KT9A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F153C20733 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1Jhc-00038y-0g for patchwork-qemu-devel@patchwork.kernel.org; Mon, 10 Feb 2020 19:47:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59878) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1Jbv-0000yu-Gc for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1Jbr-000534-If for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:07 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:59203) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j1Jbr-0004tJ-9J for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1581381663; x=1612917663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Eo7K1kCF6R8uiK43nKK4ng2GnOHtoFZTcAxkHh+nxY=; b=y717KT9A+f6xk02kA95Vx+oRVuxlE7KJJiCkIaAzvNzu7iDJzorqcShP JCkLJFmjJOy1xa3YMH9Cw0t6yzgtjIihUQjsqJc0Fit/VRqZX9fRR+lmk qb7H80v1YhTi2Ku2Hu+HyLoTtqx6sKfQjRCOl63IZ4B+OsTRx/w5J/F8u g=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 10 Feb 2020 16:40:59 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 10 Feb 2020 16:40:58 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id F11071B27; Mon, 10 Feb 2020 18:40:57 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH 10/66] Hexagon register fields Date: Mon, 10 Feb 2020 18:39:48 -0600 Message-Id: <1581381644-13678-11-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.c | 28 +++++++++++ target/hexagon/reg_fields.h | 40 +++++++++++++++ target/hexagon/reg_fields_def.h | 109 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 target/hexagon/reg_fields.c create mode 100644 target/hexagon/reg_fields.h create mode 100644 target/hexagon/reg_fields_def.h diff --git a/target/hexagon/reg_fields.c b/target/hexagon/reg_fields.c new file mode 100644 index 0000000..983655e --- /dev/null +++ b/target/hexagon/reg_fields.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include "reg_fields.h" + +reg_field_t reg_field_info[] = { +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ + {NAME, START, WIDTH, DESCRIPTION}, +#include "reg_fields_def.h" + {NULL, 0, 0} +#undef DEF_REG_FIELD +}; + diff --git a/target/hexagon/reg_fields.h b/target/hexagon/reg_fields.h new file mode 100644 index 0000000..79857c5 --- /dev/null +++ b/target/hexagon/reg_fields.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef REGS_H +#define REGS_H + +#define NUM_GEN_REGS 32 + +typedef struct { + const char *name; + int offset; + int width; + const char *description; +} reg_field_t; + +extern reg_field_t reg_field_info[]; + +enum reg_fields_enum { +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ + TAG, +#include "reg_fields_def.h" + NUM_REG_FIELDS +#undef DEF_REG_FIELD +}; + +#endif diff --git a/target/hexagon/reg_fields_def.h b/target/hexagon/reg_fields_def.h new file mode 100644 index 0000000..095a776 --- /dev/null +++ b/target/hexagon/reg_fields_def.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * For registers that have individual fields, explain them here + * DEF_REG_FIELD(tag, + * name, + * bit start offset, + * width, + * description + */ + +/* USR fields */ +DEF_REG_FIELD(USR_OVF, + "ovf", 0, 1, + "Sticky Saturation Overflow - " + "Set when saturation occurs while executing instruction that specifies " + "optional saturation, remains set until explicitly cleared by a USR=Rs " + "instruction.") +DEF_REG_FIELD(USR_FPINVF, + "fpinvf", 1, 1, + "Floating-point IEEE Invalid Sticky Flag.") +DEF_REG_FIELD(USR_FPDBZF, + "fpdbzf", 2, 1, + "Floating-point IEEE Divide-By-Zero Sticky Flag.") +DEF_REG_FIELD(USR_FPOVFF, + "fpovff", 3, 1, + "Floating-point IEEE Overflow Sticky Flag.") +DEF_REG_FIELD(USR_FPUNFF, + "fpunff", 4, 1, + "Floating-point IEEE Underflow Sticky Flag.") +DEF_REG_FIELD(USR_FPINPF, + "fpinpf", 5, 1, + "Floating-point IEEE Inexact Sticky Flag.") + +DEF_REG_FIELD(USR_LPCFG, + "lpcfg", 8, 2, + "Hardware Loop Configuration: " + "Number of loop iterations (0-3) remaining before pipeline predicate " + "should be set.") +DEF_REG_FIELD(USR_PKTCNT_U, + "pktcnt_u", 10, 1, + "Enable packet counting in User mode.") +DEF_REG_FIELD(USR_PKTCNT_G, + "pktcnt_g", 11, 1, + "Enable packet counting in Guest mode.") +DEF_REG_FIELD(USR_PKTCNT_M, + "pktcnt_m", 12, 1, + "Enable packet counting in Monitor mode.") +DEF_REG_FIELD(USR_HFD, + "hfd", 13, 2, + "Two bits that let the user control the amount of L1 hardware data cache " + "prefetching (up to 4 cache lines): " + "00: No prefetching, " + "01: Prefetch Loads with post-updating address mode when execution is " + "within a hardware loop, " + "10: Prefetch any hardware-detected striding Load when execution is within " + "a hardware loop, " + "11: Prefetch any hardware-detected striding Load.") +DEF_REG_FIELD(USR_HFI, + "hfi", 15, 2, + "Two bits that let the user control the amount of L1 instruction cache " + "prefetching. " + "00: No prefetching, " + "01: Allow prefetching of at most 1 additional cache line, " + "10: Allow prefetching of at most 2 additional cache lines.") + +DEF_REG_FIELD(USR_FPRND, + "fprnd", 22, 2, + "Rounding Mode for Floating-Point Instructions: " + "00: Round to nearest, ties to even (default), " + "01: Toward zero, " + "10: Downward (toward negative infinity), " + "11: Upward (toward positive infinity).") + +DEF_REG_FIELD(USR_FPINVE, + "fpinve", 25, 1, + "Enable trap on IEEE Invalid.") +DEF_REG_FIELD(USR_FPDBZE, + "fpdbze", 26, 1, "Enable trap on IEEE Divide-By-Zero.") +DEF_REG_FIELD(USR_FPOVFE, + "fpovfe", 27, 1, + "Enable trap on IEEE Overflow.") +DEF_REG_FIELD(USR_FPUNFE, + "fpunfe", 28, 1, + "Enable trap on IEEE Underflow.") +DEF_REG_FIELD(USR_FPINPE, + "fpinpe", 29, 1, + "Enable trap on IEEE Inexact.") +DEF_REG_FIELD(USR_PFA, + "pfa", 31, 1, + "L2 Prefetch Active: Set when non-blocking l2fetch instruction is " + "prefetching requested data, remains set until l2fetch prefetch operation " + "is completed (or not active).") /* read-only */ +