From patchwork Tue Feb 11 00:39:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11374409 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69AEE109A for ; Tue, 11 Feb 2020 00:50:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F20A20733 for ; Tue, 11 Feb 2020 00:50:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="u2FYeSN0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F20A20733 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1JlA-0000G6-C1 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 10 Feb 2020 19:50:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59840) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1Jbu-0000yd-RU for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1Jbr-00054C-NS for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:06 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:59208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j1Jbr-0004uP-EM for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1581381663; x=1612917663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rFpDTN41TAWs+0TnNRe2g260zl8j8HDVS51hI+iCRm8=; b=u2FYeSN03VrNrxagbB9lrDjv9xWV+qEfBV6SmR9yOLwQzc7YyayySDnx 4dtNwMVjXIMSp3PHehlEffaq4ddyWa5jQ0UOcvrqgcrguplj2DjJwZvdJ HHWD58556bC7GVabFQSloDQydyM1nJsko139s1g+ZH9LwUoaeQ0xB1Y+B g=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 10 Feb 2020 16:40:59 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg03-sd.qualcomm.com with ESMTP; 10 Feb 2020 16:40:59 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 311D71B42; Mon, 10 Feb 2020 18:40:59 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH 18/66] Hexagon instruction class definitions Date: Mon, 10 Feb 2020 18:39:56 -0600 Message-Id: <1581381644-13678-19-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Imported from the Hexagon architecture library Signed-off-by: Taylor Simpson --- target/hexagon/imported/iclass.def | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 target/hexagon/imported/iclass.def diff --git a/target/hexagon/imported/iclass.def b/target/hexagon/imported/iclass.def new file mode 100644 index 0000000..4bd4b97 --- /dev/null +++ b/target/hexagon/imported/iclass.def @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* DEF_*(TYPE,SLOTS,UNITS) */ +DEF_PP_ICLASS32(EXTENDER,0123,LDST|SUNIT|MUNIT) /* 0 */ +DEF_PP_ICLASS32(CJ,0123,CTRLFLOW) /* 1 */ +DEF_PP_ICLASS32(NCJ,01,LDST|CTRLFLOW) /* 2 */ +DEF_PP_ICLASS32(V4LDST,01,LDST) /* 3 */ +DEF_PP_ICLASS32(V2LDST,01,LDST) /* 4 */ +DEF_PP_ICLASS32(J,0123,CTRLFLOW) /* 5 */ +DEF_PP_ICLASS32(CR,3,SUNIT) /* 6 */ +DEF_PP_ICLASS32(ALU32_2op,0123,LDST|SUNIT|MUNIT) /* 7 */ +DEF_PP_ICLASS32(S_2op,23,SUNIT|MUNIT) /* 8 */ +DEF_PP_ICLASS32(LD,01,LDST) /* 9 */ +DEF_PP_ICLASS32(ST,01,LDST) /* 10 */ +DEF_PP_ICLASS32(ALU32_ADDI,0123,LDST|SUNIT|MUNIT) /* 11 */ +DEF_PP_ICLASS32(S_3op,23,SUNIT|MUNIT) /* 12 */ +DEF_PP_ICLASS32(ALU64,23,SUNIT|MUNIT) /* 13 */ +DEF_PP_ICLASS32(M,23,SUNIT|MUNIT) /* 14 */ +DEF_PP_ICLASS32(ALU32_3op,0123,LDST|SUNIT|MUNIT) /* 15 */ + +DEF_EE_ICLASS32(EE0,01,INVALID) /* 0 */ +DEF_EE_ICLASS32(EE1,01,INVALID) /* 1 */ +DEF_EE_ICLASS32(EE2,01,INVALID) /* 2 */ +DEF_EE_ICLASS32(EE3,01,INVALID) /* 3 */ +DEF_EE_ICLASS32(EE4,01,INVALID) /* 4 */ +DEF_EE_ICLASS32(EE5,01,INVALID) /* 5 */ +DEF_EE_ICLASS32(EE6,01,INVALID) /* 6 */ +DEF_EE_ICLASS32(EE7,01,INVALID) /* 7 */ +DEF_EE_ICLASS32(EE8,01,INVALID) /* 8 */ +DEF_EE_ICLASS32(EE9,01,INVALID) /* 9 */ +DEF_EE_ICLASS32(EEA,01,INVALID) /* 10 */ +DEF_EE_ICLASS32(EEB,01,INVALID) /* 11 */ +DEF_EE_ICLASS32(EEC,01,INVALID) /* 12 */ +DEF_EE_ICLASS32(EED,01,INVALID) /* 13 */ +DEF_EE_ICLASS32(EEE,01,INVALID) /* 14 */ +DEF_EE_ICLASS32(EEF,01,INVALID) /* 15 */ +