From patchwork Tue Feb 11 00:39:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11374459 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69EE8921 for ; Tue, 11 Feb 2020 00:54:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30EB92072C for ; Tue, 11 Feb 2020 00:54:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Gsp1ofLJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 30EB92072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1JpA-0007B3-C8 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 10 Feb 2020 19:54:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59847) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1Jbu-0000yf-UE for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1Jbr-000500-5n for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:06 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:59208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j1Jbq-0004uP-Oh for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:41:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1581381662; x=1612917662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+2eSOLkXxiaKYxSAUfJ7Trhq3ZkpiHa9WIfcb1oMvb0=; b=Gsp1ofLJ2Cci+VG2KSim74SlSQBtL7j97QLi28BR5roOxRew4JqKRFvo 3RXY80/pmRwwiBPWjozPEdHuaqC2mHsXQoQO0MGCkvlsFwL+Ne+CaFfSw YdM1xosjhhMyFqwgVavJVDU4AwCGy3SGP8nvgWP7N5SF4SKeuA4xOMjiv E=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 10 Feb 2020 16:40:58 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg03-sd.qualcomm.com with ESMTP; 10 Feb 2020 16:40:58 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 8300C1B76; Mon, 10 Feb 2020 18:40:57 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH 06/66] Hexagon CPU Scalar Core Helpers Date: Mon, 10 Feb 2020 18:39:44 -0600 Message-Id: <1581381644-13678-7-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 37 ++++ target/hexagon/op_helper.c | 432 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 469 insertions(+) create mode 100644 target/hexagon/helper.h create mode 100644 target/hexagon/op_helper.c diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h new file mode 100644 index 0000000..5dc0f71 --- /dev/null +++ b/target/hexagon/helper.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "helper_overrides.h" + +DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_1(debug_start_packet, void, env) +DEF_HELPER_2(new_value, s32, env, int) +DEF_HELPER_3(debug_check_store_width, void, env, int, int) +DEF_HELPER_3(debug_commit_end, void, env, int, int) +DEF_HELPER_3(sfrecipa_val, s32, env, s32, s32) +DEF_HELPER_3(sfrecipa_pred, s32, env, s32, s32) +DEF_HELPER_2(sfinvsqrta_val, s32, env, s32) +DEF_HELPER_2(sfinvsqrta_pred, s32, env, s32) +DEF_HELPER_4(vacsh_val, s64, env, s64, s64, s64) +DEF_HELPER_4(vacsh_pred, s32, env, s64, s64, s64) + +#define DEF_QEMU(TAG, SHORTCODE, HELPER, GENFN, HELPFN) HELPER +#include "qemu_def_generated.h" +#undef DEF_QEMU + +DEF_HELPER_2(debug_value, void, env, s32) +DEF_HELPER_2(debug_value_i64, void, env, s64) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c new file mode 100644 index 0000000..66ccd20 --- /dev/null +++ b/target/hexagon/op_helper.c @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include +#include +#include "qemu/osdep.h" +#include "qemu.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-op.h" +#include "cpu.h" +#include "internal.h" +#include "macros.h" +#include "arch.h" +#include "fma_emu.h" +#include "conv_emu.h" + +#if COUNT_HEX_HELPERS +#include "opcodes.h" + +typedef struct { + int count; + const char *tag; +} helper_count_t; + +helper_count_t helper_counts[] = { +#define OPCODE(TAG) { 0, #TAG }, +#include "opcodes_def_generated.h" +#undef OPCODE + { 0, NULL } +}; + +#define COUNT_HELPER(TAG) \ + do { \ + helper_counts[(TAG)].count++; \ + } while (0) + +void print_helper_counts(void) +{ + helper_count_t *p; + + printf("HELPER COUNTS\n"); + for (p = helper_counts; p->tag; p++) { + if (p->count) { + printf("\t%d\t\t%s\n", p->count, p->tag); + } + } +} +#else +#define COUNT_HELPER(TAG) /* Nothing */ +#endif + +/* Exceptions processing helpers */ +static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env, + uint32_t exception, + uintptr_t pc) +{ + CPUState *cs = CPU(hexagon_env_get_cpu(env)); + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); + cs->exception_index = exception; + cpu_loop_exit_restore(cs, pc); +} + +void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exception) +{ + do_raise_exception_err(env, exception, 0); +} + +static inline void log_reg_write(CPUHexagonState *env, int rnum, + target_ulong val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")", + rnum, val, val); + if (env->slot_cancelled & (1 << slot)) { + HEX_DEBUG_LOG(" CANCELLED"); + } + if (val == env->gpr[rnum]) { + HEX_DEBUG_LOG(" NO CHANGE"); + } + HEX_DEBUG_LOG("\n"); + if (!(env->slot_cancelled & (1 << slot))) { + env->new_value[rnum] = val; + } +} + +static __attribute__((unused)) +inline void log_reg_write_pair(CPUHexagonState *env, int rnum, + int64_t val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val); + log_reg_write(env, rnum, val & 0xFFFFFFFF, slot); + log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot); +} + +static inline void log_pred_write(CPUHexagonState *env, int pnum, + target_ulong val) +{ + HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld + " (0x" TARGET_FMT_lx ")\n", + pnum, val, val); + + /* Multiple writes to the same preg are and'ed together */ + if (env->pred_written[pnum]) { + env->new_pred_value[pnum] &= val & 0xff; + } else { + env->new_pred_value[pnum] = val & 0xff; + env->pred_written[pnum] = 1; + } +} + +static inline void log_store32(CPUHexagonState *env, target_ulong addr, + target_ulong val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld + " [0x" TARGET_FMT_lx "])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data32 = val; +} + +static inline void log_store64(CPUHexagonState *env, target_ulong addr, + int64_t val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data64 = val; +} + +static inline void write_new_pc(CPUHexagonState *env, target_ulong addr) +{ + HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); + + /* + * If more than one branch it taken in a packet, only the first one + * is actually done. + */ + if (env->branch_taken) { + HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " + "ignoring the second one\n"); + } else { + fCHECK_PCALIGN(addr); + env->branch_taken = 1; + env->next_PC = addr; + } +} + +/* Handy place to set a breakpoint */ +void HELPER(debug_start_packet)(CPUHexagonState *env) +{ + HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", + env->gpr[HEX_REG_PC]); + + int i; + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + env->reg_written[i] = 0; + } +} + +/* + * This helper is needed when the rnum has already been turned into a TCGv, + * so we can't just do tcg_gen_mov_tl(result, hex_new_value[rnum]); + */ +int32_t HELPER(new_value)(CPUHexagonState *env, int rnum) +{ + return env->new_value[rnum]; +} + +static inline int32_t new_pred_value(CPUHexagonState *env, int pnum) +{ + return env->new_pred_value[pnum]; +} + +/* Checks for bookkeeping errors between disassembly context and runtime */ +void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) +{ + if (env->mem_log_stores[slot].width != check) { + HEX_DEBUG_LOG("ERROR: %d != %d\n", + env->mem_log_stores[slot].width, check); + g_assert_not_reached(); + } +} + +static void print_store(CPUHexagonState *env, int slot) +{ + if (!(env->slot_cancelled & (1 << slot))) { + size1u_t width = env->mem_log_stores[slot].width; + if (width == 1) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xff; + HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %d (0x%02x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 2) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xffff; + HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %d (0x%04x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 4) { + size4u_t data = env->mem_log_stores[slot].data32; + HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %d (0x%08x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 8) { + HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu (0x%016lx)\n", + env->mem_log_stores[slot].va, + env->mem_log_stores[slot].data64, + env->mem_log_stores[slot].data64); + } else { + HEX_DEBUG_LOG("\tBad store width %d\n", width); + g_assert_not_reached(); + } + } +} + +/* This function is a handy place to set a breakpoint */ +void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) +{ + bool reg_printed = false; + bool pred_printed = false; + int i; + + HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", + env->this_PC); + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + if (env->reg_written[i]) { + if (!reg_printed) { + HEX_DEBUG_LOG("Regs written\n"); + reg_printed = true; + } + HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx " )\n", + i, env->new_value[i], env->new_value[i]); + } + } + + for (i = 0; i < NUM_PREGS; i++) { + if (env->pred_written[i]) { + if (!pred_printed) { + HEX_DEBUG_LOG("Predicates written\n"); + pred_printed = true; + } + HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", + i, env->new_pred_value[i]); + } + } + + if (has_st0 || has_st1) { + HEX_DEBUG_LOG("Stores\n"); + if (has_st0) { + print_store(env, 0); + } + if (has_st1) { + print_store(env, 1); + } + } + + HEX_DEBUG_LOG("Next PC = 0x%x\n", env->next_PC); + HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx + ", insn = " TARGET_FMT_lx + ", hvx = " TARGET_FMT_lx "\n", + env->gpr[HEX_REG_QEMU_PKT_CNT], + env->gpr[HEX_REG_QEMU_INSN_CNT], + env->gpr[HEX_REG_QEMU_HVX_CNT]); + +} + +/* + * sfrecipa, sfinvsqrta, vacsh have two results + * r0,p0=sfrecipa(r1,r2) + * r0,p0=sfinvsqrta(r1) + * r1:0,p0=vacsh(r3:2,r5:4) + * Since helpers can only return a single value, we have two helpers + * for each of these. They each contain basically the same code (copy/pasted + * from the arch library), but one returns the register and the other + * returns the predicate. + */ +int32_t HELPER(sfrecipa_val)(CPUHexagonState *env, int32_t RsV, int32_t RtV) +{ + /* int32_t PeV; Not needed to compute value */ + int32_t RdV; + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_RECIP_COMMON(RsV, RtV, RdV, adjust)) { + /* PeV = adjust; Not needed to compute value */ + idx = (RtV >> 16) & 0x7f; + mant = (fSF_RECIP_LOOKUP(idx) << 15) | 1; + exp = fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1; + RdV = fMAKESF(fGETBIT(31, RtV), exp, mant); + } + return RdV; +} + +int32_t HELPER(sfrecipa_pred)(CPUHexagonState *env, int32_t RsV, int32_t RtV) +{ + int32_t PeV = 0; + int32_t RdV; + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_RECIP_COMMON(RsV, RtV, RdV, adjust)) { + PeV = adjust; + idx = (RtV >> 16) & 0x7f; + mant = (fSF_RECIP_LOOKUP(idx) << 15) | 1; + exp = fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1; + RdV = fMAKESF(fGETBIT(31, RtV), exp, mant); + } + return PeV; +} + +int32_t HELPER(sfinvsqrta_val)(CPUHexagonState *env, int32_t RsV) +{ + /* int32_t PeV; Not needed for val version */ + int32_t RdV; + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_INVSQRT_COMMON(RsV, RdV, adjust)) { + /* PeV = adjust; Not needed for val version */ + idx = (RsV >> 17) & 0x7f; + mant = (fSF_INVSQRT_LOOKUP(idx) << 15); + exp = fSF_BIAS() - ((fSF_GETEXP(RsV) - fSF_BIAS()) >> 1) - 1; + RdV = fMAKESF(fGETBIT(31, RsV), exp, mant); + } + return RdV; +} + +int32_t HELPER(sfinvsqrta_pred)(CPUHexagonState *env, int32_t RsV) +{ + int32_t PeV = 0; + int32_t RdV; + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_INVSQRT_COMMON(RsV, RdV, adjust)) { + PeV = adjust; + idx = (RsV >> 17) & 0x7f; + mant = (fSF_INVSQRT_LOOKUP(idx) << 15); + exp = fSF_BIAS() - ((fSF_GETEXP(RsV) - fSF_BIAS()) >> 1) - 1; + RdV = fMAKESF(fGETBIT(31, RsV), exp, mant); + } + return PeV; +} + +int64_t HELPER(vacsh_val)(CPUHexagonState *env, + int64_t RxxV, int64_t RssV, int64_t RttV) +{ + int32_t PeV = 0; + fHIDE(int i;) + fHIDE(int xv;) + fHIDE(int sv;) + fHIDE(int tv;) + for (i = 0; i < 4; i++) { + xv = (int)fGETHALF(i, RxxV); + sv = (int)fGETHALF(i, RssV); + tv = (int)fGETHALF(i, RttV); + xv = xv + tv; + sv = sv - tv; + fSETBIT(i * 2, PeV, (xv > sv)); + fSETBIT(i * 2 + 1, PeV, (xv > sv)); + fSETHALF(i, RxxV, fSATH(fMAX(xv, sv))); + } + return RxxV; +} + +int32_t HELPER(vacsh_pred)(CPUHexagonState *env, + int64_t RxxV, int64_t RssV, int64_t RttV) +{ + int32_t PeV = 0; + fHIDE(int i;) + fHIDE(int xv;) + fHIDE(int sv;) + fHIDE(int tv;) + for (i = 0; i < 4; i++) { + xv = (int)fGETHALF(i, RxxV); + sv = (int)fGETHALF(i, RssV); + tv = (int)fGETHALF(i, RttV); + xv = xv + tv; + sv = sv - tv; + fSETBIT(i * 2, PeV, (xv > sv)); + fSETBIT(i * 2 + 1, PeV, (xv > sv)); + fSETHALF(i, RxxV, fSATH(fMAX(xv, sv))); + } + return PeV; +} + +/* Helpful for printing intermediate values within instructions */ +void HELPER(debug_value)(CPUHexagonState *env, int32_t value) +{ + HEX_DEBUG_LOG("value = 0x%x\n", value); +} + +void HELPER(debug_value_i64)(CPUHexagonState *env, int64_t value) +{ + HEX_DEBUG_LOG("value = 0x%lx\n", value); +} + +static void cancel_slot(CPUHexagonState *env, uint32_t slot) +{ + HEX_DEBUG_LOG("Slot %d cancelled\n", slot); + env->slot_cancelled |= (1 << slot); +} + +/* These macros can be referenced in the generated helper functions */ +#define warn(...) /* Nothing */ +#define fatal(...) g_assert_not_reached(); + +#define BOGUS_HELPER(tag) \ + printf("ERROR: bogus helper: " #tag "\n") + +#define DEF_QEMU(TAG, SHORTCODE, HELPER, GENFN, HELPFN) HELPFN +#include "qemu_def_generated.h" +#undef DEF_QEMU +