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Thu, 20 Feb 2020 23:46:40 -0800 Received: from xsj-pvapsmtp01 (xsj-mail.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01L7keGm018620; Thu, 20 Feb 2020 23:46:40 -0800 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j531D-0006CP-TG; Thu, 20 Feb 2020 23:46:40 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 9A58F13C0374; Fri, 21 Feb 2020 13:12:15 +0530 (IST) From: Sai Pavan Boddu To: "Edgar E . Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v2 1/3] arm_gic: Mask the un-supported priority bits Date: Fri, 21 Feb 2020 13:12:05 +0530 Message-Id: <1582270927-2568-2-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(376002)(39850400004)(396003)(136003)(346002)(199004)(189003)(8936002)(426003)(70206006)(336012)(70586007)(42186006)(316002)(6266002)(2616005)(110136005)(2906002)(5660300002)(356004)(6666004)(186003)(4326008)(478600001)(26005)(81156014)(8676002)(81166006)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR02MB2278; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2ebfaa9b-1b2d-4b3f-4c37-08d7b6a233bf X-MS-TrafficTypeDiagnostic: CY4PR02MB2278: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:626; X-Forefront-PRVS: 0320B28BE1 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7XRKzyXILk4oN+5NbGc4zRp8AzepNC9swEz6X+3tnuzmBZRUkfvsKerOf7ZJ/8vCaY5pvOFW8rqY9broeOEbSziEe+Z9NdjdGVdZSzDQctytuSDyqCDOg6Gw+3e19DMo/Q8CKLhJKPSiuZX8dRdFOOqFeEC5LXKIF3Zv6VPKj64xst/+0ziidWrMRQncXgNZ4PU3R+NqooaGflvijHhch0ZursioOz3NpM6it2/L/344cS5bOK+SI/7JNjunMOEI8wUcC4aUp843MOWoPurKRLOyliAKhMcpqAQzNk4uM39mx4Y6LnOgqHZM7Y/WMPIuomCZlHDdQmSbB60KWk10mi3w2SEikkmOyI7v/RFVlOpUyt4dy4pZpk7zYW2Sd/swqKXadg5gd5owKFT+9ESm54foc+3uIvFiyrncIwlWc820GL/coCljnJWunNMYXsFT X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2020 07:46:46.3875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ebfaa9b-1b2d-4b3f-4c37-08d7b6a233bf X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2278 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.223.70 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits are read as zeros(RAZ). Signed-off-by: Sai Pavan Boddu --- hw/intc/arm_gic.c | 26 ++++++++++++++++++++++++-- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7b..dec8767 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) return ret; } +static uint32_t gic_fullprio_mask(GICState *s, int cpu) +{ + /* + * Return a mask word which clears the unimplemented priority + * bits from a priority value for an interrupt. (Not to be + * confused with the group priority, whose mask depends on BPR.) + */ + int unimpBits; + + if (gic_is_vcpu(cpu)) { + unimpBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; + } else { + unimpBits = 8 - s->n_prio_bits; + } + return ~0U << unimpBits; +} + void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { @@ -669,7 +686,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, } prio = (prio << 1) & 0xff; /* Non-secure view */ } - return prio; + return prio & gic_fullprio_mask(s, cpu); } static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, @@ -684,7 +701,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, return; } } - s->priority_mask[cpu] = pmask; + s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); } static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) @@ -2055,6 +2072,11 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) return; } + if (s->n_prio_bits > 8) { + error_setg(errp, "num-priority-bits cannot be greater than 8"); + return; + } + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if * enabled, virtualization extensions related interfaces (main virtual * interface (s->vifaceiomem[0]) and virtual CPU interface). diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7..7b44d56 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index b5585fe..6e0d6b8 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -96,6 +96,7 @@ typedef struct GICState { uint16_t priority_mask[GIC_NCPU_VCPU]; uint16_t running_priority[GIC_NCPU_VCPU]; uint16_t current_pending[GIC_NCPU_VCPU]; + uint32_t n_prio_bits; /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary point