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Thu, 20 Feb 2020 23:46:41 -0800 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01L7kfvl017851; Thu, 20 Feb 2020 23:46:41 -0800 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j531E-0006CW-QP; Thu, 20 Feb 2020 23:46:41 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 801DE13C0FD3; Fri, 21 Feb 2020 13:12:16 +0530 (IST) From: Sai Pavan Boddu To: "Edgar E . Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v2 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5 Date: Fri, 21 Feb 2020 13:12:06 +0530 Message-Id: <1582270927-2568-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582270927-2568-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(376002)(346002)(39850400004)(396003)(136003)(189003)(199004)(2616005)(4744005)(336012)(186003)(110136005)(81156014)(26005)(4326008)(5660300002)(2906002)(81166006)(42186006)(316002)(8676002)(8936002)(426003)(70206006)(70586007)(6266002)(6666004)(356004)(36756003)(478600001); DIR:OUT; SFP:1101; SCL:1; SRVR:CH2PR02MB7045; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4fb82471-59c8-478b-c97d-08d7b6a23450 X-MS-TrafficTypeDiagnostic: CH2PR02MB7045: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:161; X-Forefront-PRVS: 0320B28BE1 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AjkcSiGdRB6vtKdoXfMH5k9nV1su3D6M/JzaqWGe/Z44e8xgkySyohMjqBrss0RFWmzJ298k+9W2PYnzAbzUruJTB++QXbuRB8S/3OcK4ZKOtSvjzhoB6qguISyztYjz/thN8omlV9wzA2uMbFhB4fACYGIZGHI4YeBbcJqd/NqKV3GdDp8zv8aqF2g6V78LQi7qEqUWy4Zp9O20i4QZu5WaWq8pMmRAfNKL+asBxdJ2cYjwDDlWxmv3viz4Gxg5UPnwenhSzuUdXQnsGHeI1y/SLMpqHs81NZKHYXdNjS2ELY+3XJ7mM25wLMkKeybvX317xjbQ16dl8uCILEOdoB5K3BJ0SGRqBg4Bjrqxhh9r1Rwg+jIIzdleBG9gm4OR4gF8328c3DFX0pTyz12Vwz3mQkSVJCciqLHLOOIbp/2vU7M0X7vK1vWjNvfIgZO4 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2020 07:46:47.3589 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4fb82471-59c8-478b-c97d-08d7b6a23450 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB7045 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.243.47 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" All A9 CPUs have a GIC with 5 bits of priority. Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/cpu/a9mpcore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a..b4f6a7e 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -16,6 +16,8 @@ #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#define A9_GIC_NUM_PRIORITY_BITS 5 + static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s = (A9MPPrivState *)opaque; @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do.