From patchwork Fri Feb 28 16:43:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11412945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26CD8924 for ; Fri, 28 Feb 2020 17:08:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F250E24691 for ; Fri, 28 Feb 2020 17:08:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="uvP69USt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F250E24691 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7j7f-0007dm-45 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 28 Feb 2020 12:08:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58144) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ilL-0004JJ-QT for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ilJ-0006Qx-Rd for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:19 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:13235) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7ilJ-0005U6-C2 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908317; x=1614444317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J/CNIescHakrSYwZeabTtA5yBzDGVHYDq4Bf/AC12VI=; b=uvP69USt9fkFYa2WFedthpy3O0KNdBpFvzsdHNSACBwdGwmBu5zJ2IWr 9ZsrfoTt4uCj91y0jcRXHg413wr/UTBrXCGiJSl+GayRc6jWyb+A5FmpF hGS5V4Xvh/PjboIxFq02ki/bJzVyN8y+651mSUBlrVeCiQvnHfma42EU1 8=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Feb 2020 08:44:31 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 28 Feb 2020 08:44:30 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 37565119A; Fri, 28 Feb 2020 10:44:30 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Date: Fri, 28 Feb 2020 10:43:24 -0600 Message-Id: <1582908244-304-29-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.38 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Tested-by: Philippe Mathieu-Daudé --- target/hexagon/gen_dectree_import.c | 205 ++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 target/hexagon/gen_dectree_import.c diff --git a/target/hexagon/gen_dectree_import.c b/target/hexagon/gen_dectree_import.c new file mode 100644 index 0000000..4dfd4d4 --- /dev/null +++ b/target/hexagon/gen_dectree_import.c @@ -0,0 +1,205 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * This program generates the encodings file that is processed by + * the dectree.py script to produce the decoding tree. We use the C + * preprocessor to manipulate the files imported from the Hexagon + * architecture library. + */ +#include +#include +#include "opcodes.h" + +#define STRINGIZE(X) #X + +const char *opcode_names[] = { +#define OPCODE(IID) STRINGIZE(IID) +#include "opcodes_def_generated.h" + NULL +#undef OPCODE +}; + +char *opcode_syntax[XX_LAST_OPCODE]; + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + * HVX instructions have the following form + * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)", + * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE,A_NOTE_MPY_RESOURCE), + * "Insert Word Scalar into Vector", + * VxV.uw[0] = RtV;) + */ +void opcode_init() +{ +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + opcode_syntax[TAG] = BEH; +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + opcode_syntax[TAG] = BEH; +#include "imported/allidefs.def" +#undef Q6INSN +#undef EXTINSN +} + +const char *opcode_rregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) RREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +const char *opcode_wregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) WREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +opcode_encoding_t opcode_encodings[] = { +#define DEF_ENC32(TAG, ENCSTR) \ + [TAG] = { .encoding = ENCSTR }, +#define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#include "imported/encode.def" +#undef DEF_ENC32 +#undef DEF_ENC_SUBINSN +#undef DEF_EXT_ENC +}; + +static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = { + "NORMAL", + "16BIT", + "SUBINSN_A", + "SUBINSN_L1", + "SUBINSN_L2", + "SUBINSN_S1", + "SUBINSN_S2", + "EXT_noext", + "EXT_mmvec", +}; + +static const char *get_opcode_enc(int opcode) +{ + const char *tmp = opcode_encodings[opcode].encoding; + if (tmp == NULL) { + tmp = "MISSING ENCODING"; + } + return tmp; +} + +static const char *get_opcode_enc_class(int opcode) +{ + const char *tmp = opcode_encodings[opcode].encoding; + if (tmp == NULL) { + char *test = "V6_"; /* HVX */ + char *name = (char *)opcode_names[opcode]; + if (strncmp(name, test, strlen(test)) == 0) { + return "EXT_mmvec"; + } + } + return opcode_enc_class_names[opcode_encodings[opcode].enc_class]; +} + +static void gen_iset_table(FILE *out) +{ + int i; + + fprintf(out, "iset = {\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\' : {\n", opcode_names[i]); + fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]); + fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]); + fprintf(out, "\t\t\'rregs\' : \'%s\',\n", opcode_rregs[i]); + fprintf(out, "\t\t\'wregs\' : \'%s\',\n", opcode_wregs[i]); + fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i)); + fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i)); + fprintf(out, "\t},\n"); + } + fprintf(out, "};\n\n"); +} + +static void gen_tags_list(FILE *out) +{ + int i; + + fprintf(out, "tags = [\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\',\n", opcode_names[i]); + } + fprintf(out, "];\n\n"); +} + +static void gen_enc_ext_spaces_table(FILE *out) +{ + fprintf(out, "enc_ext_spaces = {\n"); +#define DEF_EXT_SPACE(SPACEID, ENCSTR) \ + fprintf(out, "\t\'%s\' : \'%s\',\n", #SPACEID, ENCSTR); +#include "imported/encode.def" +#undef DEF_EXT_SPACE + fprintf(out, "};\n\n"); +} + +static void gen_subinsn_groupings_table(FILE *out) +{ + fprintf(out, "subinsn_groupings = {\n"); +#define DEF_PACKED32(TAG, TYPEA, TYPEB, ENCSTR) \ + do { \ + fprintf(out, "\t\'%s\' : {\n", #TAG); \ + fprintf(out, "\t\t\'name\' : \'%s\',\n", #TAG); \ + fprintf(out, "\t\t\'class_a\' : \'%s\',\n", #TYPEA); \ + fprintf(out, "\t\t\'class_b\' : \'%s\',\n", #TYPEB); \ + fprintf(out, "\t\t\'enc\' : \'%s\',\n", ENCSTR); \ + fprintf(out, "\t},\n"); \ + } while (0); +#include "imported/encode.def" +#undef DEF_PACKED32 + fprintf(out, "};\n\n"); +} + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n"); + return -1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return -1; + } + + opcode_init(); + gen_iset_table(outfile); + gen_tags_list(outfile); + gen_enc_ext_spaces_table(outfile); + gen_subinsn_groupings_table(outfile); + + fclose(outfile); + return 0; +}