From patchwork Fri Feb 28 16:43:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11413055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0299E1395 for ; Fri, 28 Feb 2020 17:29:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CED4A24699 for ; Fri, 28 Feb 2020 17:29:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="zR1fP3j4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CED4A24699 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jRf-0007bh-U4 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 28 Feb 2020 12:29:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58099) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ilJ-0004EK-NF for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ilI-0006Pi-Em for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:17 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:27049) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7ikw-0005V5-8R for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908294; x=1614444294; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OxyAc5vby+TObY6b7PeXziCqzZoxlQP+3+9J1vLPfv8=; b=zR1fP3j49/iWhcvSwI1njVdVVBKhCaqS/EWxr73ydq7dY9ZNp5TF25ZE plNaaEig/JicXTWSgjEhbQxPtM7MmKztlJcHmd32Aqz83j+jqd5gYZQYn HJXRJORmvbxFmLUAqeDzYY/gwJfcDoHzACpUR2WaMBDnjzjfLdqVnNMUm s=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 28 Feb 2020 08:44:32 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 28 Feb 2020 08:44:31 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id E6C6A1191; Fri, 28 Feb 2020 10:44:30 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Date: Fri, 28 Feb 2020 10:43:32 -0600 Message-Id: <1582908244-304-37-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Helpers for store instructions Signed-off-by: Taylor Simpson --- target/hexagon/genptr_helpers.h | 77 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h index c0e4c39..0e2d7b9 100644 --- a/target/hexagon/genptr_helpers.h +++ b/target/hexagon/genptr_helpers.h @@ -386,4 +386,81 @@ static inline void gen_store_conditional8(CPUHexagonState *env, tcg_temp_free(tmp); } +static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_mov_tl(hex_store_val32[slot], src); +} + +static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(slot); + gen_store32(vaddr, src, 1, slot); + tcg_temp_free(tmp); + ctx->ctx_store_width[slot] = 1; +} + +static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(src); + gen_store1(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(slot); + gen_store32(vaddr, src, 2, slot); + tcg_temp_free(tmp); + ctx->ctx_store_width[slot] = 2; +} + +static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(src); + gen_store2(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(slot); + gen_store32(vaddr, src, 4, slot); + tcg_temp_free(tmp); + ctx->ctx_store_width[slot] = 4; +} + +static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(src); + gen_store4(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, + DisasContext *ctx, int slot) +{ + TCGv tmp = tcg_const_tl(slot); + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_mov_i64(hex_store_val64[slot], src); + tcg_temp_free(tmp); + ctx->ctx_store_width[slot] = 8; +} + +static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, + DisasContext *ctx, int slot) +{ + TCGv_i64 tmp = tcg_const_i64(src); + gen_store8(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free_i64(tmp); +} + #endif