[RFC,v2,40/67] Hexagon TCG generation - step 02

Message ID	1582908244-304-41-git-send-email-tsimpson@quicinc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=5hto=4Q=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2554724699 From: Taylor Simpson <tsimpson@quicinc.com> To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Date: Fri, 28 Feb 2020 10:43:36 -0600 Message-Id: <1582908244-304-41-git-send-email-tsimpson@quicinc.com> In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Precedence: list Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	Hexagon patch series \| expand [RFC,v2,00/67] Hexagon patch series [RFC,v2,01/67] Hexagon Maintainers [RFC,v2,02/67] Hexagon README [RFC,v2,03/67] Hexagon ELF Machine Definition [RFC,v2,04/67] Hexagon CPU Scalar Core Definition [RFC,v2,05/67] Hexagon register names [RFC,v2,06/67] Hexagon Disassembler [RFC,v2,07/67] Hexagon CPU Scalar Core Helpers [RFC,v2,08/67] Hexagon GDB Stub [RFC,v2,09/67] Hexagon architecture types [RFC,v2,10/67] Hexagon instruction and packet types [RFC,v2,11/67] Hexagon register fields [RFC,v2,12/67] Hexagon instruction attributes [RFC,v2,13/67] Hexagon register map [RFC,v2,14/67] Hexagon instruction/packet decode [RFC,v2,15/67] Hexagon instruction printing [RFC,v2,16/67] Hexagon arch import - instruction semantics definitions [RFC,v2,17/67] Hexagon arch import - macro definitions [RFC,v2,18/67] Hexagon arch import - instruction encoding [RFC,v2,19/67] Hexagon instruction class definitions [RFC,v2,20/67] Hexagon instruction utility functions [RFC,v2,21/67] Hexagon generator phase 1 - C preprocessor for semantics [RFC,v2,22/67] Hexagon generator phase 2 - qemu_def_generated.h [RFC,v2,23/67] Hexagon generator phase 2 - qemu_wrap_generated.h [RFC,v2,24/67] Hexagon generator phase 2 - opcodes_def_generated.h [RFC,v2,25/67] Hexagon generator phase 2 - op_attribs_generated.h [RFC,v2,26/67] Hexagon generator phase 2 - op_regs_generated.h [RFC,v2,27/67] Hexagon generator phase 2 - printinsn-generated.h [RFC,v2,28/67] Hexagon generator phase 3 - C preprocessor for decode tree [RFC,v2,29/67] Hexagon generater phase 4 - Decode tree [RFC,v2,30/67] Hexagon opcode data structures [RFC,v2,31/67] Hexagon macros to interface with the generator [RFC,v2,32/67] Hexagon macros referenced in instruction semantics [RFC,v2,33/67] Hexagon instruction classes [RFC,v2,34/67] Hexagon TCG generation helpers - step 1 [RFC,v2,35/67] Hexagon TCG generation helpers - step 2 [RFC,v2,36/67] Hexagon TCG generation helpers - step 3 [RFC,v2,37/67] Hexagon TCG generation helpers - step 4 [RFC,v2,38/67] Hexagon TCG generation helpers - step 5 [RFC,v2,39/67] Hexagon TCG generation - step 01 [RFC,v2,40/67] Hexagon TCG generation - step 02 [RFC,v2,41/67] Hexagon TCG generation - step 03 [RFC,v2,42/67] Hexagon TCG generation - step 04 [RFC,v2,43/67] Hexagon TCG generation - step 05 [RFC,v2,44/67] Hexagon TCG generation - step 06 [RFC,v2,45/67] Hexagon TCG generation - step 07 [RFC,v2,46/67] Hexagon TCG generation - step 08 [RFC,v2,47/67] Hexagon TCG generation - step 09 [RFC,v2,48/67] Hexagon TCG generation - step 10 [RFC,v2,49/67] Hexagon TCG generation - step 11 [RFC,v2,50/67] Hexagon TCG generation - step 12 [RFC,v2,51/67] Hexagon translation [RFC,v2,52/67] Hexagon Linux user emulation [RFC,v2,53/67] Hexagon build infrastructure [RFC,v2,54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition [RFC,v2,55/67] Hexagon HVX support in gdbstub [RFC,v2,56/67] Hexagon HVX import instruction encodings [RFC,v2,57/67] Hexagon HVX import semantics [RFC,v2,58/67] Hexagon HVX import macro definitions [RFC,v2,59/67] Hexagon HVX semantics generator [RFC,v2,60/67] Hexagon HVX instruction decoding [RFC,v2,61/67] Hexagon HVX instruction utility functions [RFC,v2,62/67] Hexagon HVX macros to interface with the generator [RFC,v2,63/67] Hexagon HVX macros referenced in instruction semantics [RFC,v2,64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) [RFC,v2,65/67] Hexagon HVX TCG generation [RFC,v2,66/67] Hexagon HVX translation [RFC,v2,67/67] Hexagon HVX build infrastructure

diff --git a/target/hexagon/helper_overrides.h b/target/hexagon/helper_overrides.h new file mode 100644 index 0000000..6a69fc6 --- /dev/null +++ b/target/hexagon/helper_overrides.h @@ -0,0 +1,404 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HEXAGON_HELPER_OVERRIDES_H +#define HEXAGON_HELPER_OVERRIDES_H + +/* + * Here is a primer to understand the tag names for load/store instructions + * + * Data types + * b signed byte r0 = memb(r2+#0) + * ub unsigned byte r0 = memub(r2+#0) + * h signed half word (16 bits) r0 = memh(r2+#0) + * uh unsigned half word r0 = memuh(r2+#0) + * i integer (32 bits) r0 = memw(r2+#0) + * d double word (64 bits) r1:0 = memd(r2+#0) + * + * Addressing modes + * _io indirect with offset r0 = memw(r1+#4) + * _ur absolute with register offset r0 = memw(r1<<#4+##variable) + * _rr indirect with register offset r0 = memw(r1+r4<<#2) + * gp global pointer relative r0 = memw(gp+#200) + * _sp stack pointer relative r0 = memw(r29+#12) + * _ap absolute set r0 = memw(r1=##variable) + * _pr post increment register r0 = memw(r1++m1) + * _pbr post increment bit reverse r0 = memw(r1++m1:brev) + * _pi post increment immediate r0 = memb(r1++#1) + * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0)) + * _pcr post increment circular register r0 = memw(r1++I:circ(m0)) + */ + +/* Macros for complex addressing modes */ +#define GET_EA_ap \ + do { \ + fEA_IMM(UiV); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) +#define GET_EA_pr \ + do { \ + fEA_REG(RxV); \ + fPM_M(RxV, MuV); \ + } while (0) +#define GET_EA_pbr \ + do { \ + fEA_BREVR(RxV); \ + fPM_M(RxV, MuV); \ + } while (0) +#define GET_EA_pi \ + do { \ + fEA_REG(RxV); \ + fPM_I(RxV, siV); \ + } while (0) +#define GET_EA_pci \ + do { \ + fEA_REG(RxV); \ + fPM_CIRI(RxV, siV, MuV); \ + } while (0) +#define GET_EA_pcr(SHIFT) \ + do { \ + fEA_REG(RxV); \ + fPM_CIRR(RxV, fREAD_IREG(MuV, (SHIFT)), MuV); \ + } while (0) + +/* + * Many instructions will work with just macro redefinitions + * with the caveat that they need a tmp variable to carry a + * value between them. + */ +#define fWRAP_tmp(SHORTCODE) \ + do { \ + TCGv tmp = tcg_temp_new(); \ + SHORTCODE; \ + tcg_temp_free(tmp); \ + } while (0) + +/* Byte load instructions */ +#define fWRAP_L2_loadrub_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrb_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrub_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrb_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrub_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrb_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrubgp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadrbgp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_SL1_loadrub_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_SL2_loadrb_io(GENHLPR, SHORTCODE) SHORTCODE + +/* Half word load instruction */ +#define fWRAP_L2_loadruh_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrh_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadruh_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrh_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadruh_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrh_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadruhgp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadrhgp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_SL2_loadruh_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_SL2_loadrh_io(GENHLPR, SHORTCODE) SHORTCODE + +/* Word load instructions */ +#define fWRAP_L2_loadri_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadri_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadri_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrigp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_SL1_loadri_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_SL2_loadri_sp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) + +/* Double word load instructions */ +#define fWRAP_L2_loadrd_io(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrd_ur(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L4_loadrd_rr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrdgp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) +#define fWRAP_SL2_loadrd_sp(GENHLPR, SHORTCODE) fWRAP_tmp(SHORTCODE) + +/* Instructions with multiple definitions */ +#define fWRAP_LOAD_AP(RES, SIZE, SIGN) \ + do { \ + fMUST_IMMEXT(UiV); \ + fEA_IMM(UiV); \ + fLOAD(1, SIZE, SIGN, EA, RES); \ + tcg_gen_movi_tl(ReV, UiV); \ + } while (0) + +#define fWRAP_L4_loadrub_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RdV, 1, u) +#define fWRAP_L4_loadrb_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RdV, 1, s) +#define fWRAP_L4_loadruh_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RdV, 2, u) +#define fWRAP_L4_loadrh_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RdV, 2, s) +#define fWRAP_L4_loadri_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RdV, 4, u) +#define fWRAP_L4_loadrd_ap(GENHLPR, SHORTCODE) \ + fWRAP_LOAD_AP(RddV, 8, u) + +#define fWRAP_L2_loadrub_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadrb_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadruh_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadrh_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadri_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) +#define fWRAP_L2_loadrd_pci(GENHLPR, SHORTCODE) \ + fWRAP_tmp(SHORTCODE) + +#define fWRAP_PCR(SHIFT, LOAD) \ + do { \ + TCGv ireg = tcg_temp_new(); \ + TCGv tmp = tcg_temp_new(); \ + fEA_REG(RxV); \ + fREAD_IREG(MuV, SHIFT); \ + gen_fcircadd(RxV, ireg, MuV, fREAD_CSREG(MuN)); \ + LOAD; \ + tcg_temp_free(tmp); \ + tcg_temp_free(ireg); \ + } while (0) + +#define fWRAP_L2_loadrub_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(0, fLOAD(1, 1, u, EA, RdV)) +#define fWRAP_L2_loadrb_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(0, fLOAD(1, 1, s, EA, RdV)) +#define fWRAP_L2_loadruh_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(1, fLOAD(1, 2, u, EA, RdV)) +#define fWRAP_L2_loadrh_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(1, fLOAD(1, 2, s, EA, RdV)) +#define fWRAP_L2_loadri_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(2, fLOAD(1, 4, u, EA, RdV)) +#define fWRAP_L2_loadrd_pcr(GENHLPR, SHORTCODE) \ + fWRAP_PCR(3, fLOAD(1, 8, u, EA, RddV)) + +#define fWRAP_L2_loadrub_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrub_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrub_pi(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrb_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrb_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrb_pi(GENHLPR, SHORTCODE) SHORTCODE; +#define fWRAP_L2_loadruh_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadruh_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadruh_pi(GENHLPR, SHORTCODE) SHORTCODE; +#define fWRAP_L2_loadrh_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrh_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrh_pi(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadri_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadri_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadri_pi(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrd_pr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrd_pbr(GENHLPR, SHORTCODE) SHORTCODE +#define fWRAP_L2_loadrd_pi(GENHLPR, SHORTCODE) SHORTCODE + +/* + * These instructions load 2 bytes and places them in + * two halves of the destination register. + * The GET_EA macro determines the addressing mode. + * The fGB macro determines whether to zero-extend or + * sign-extend. + */ +#define fWRAP_loadbXw2(GET_EA, fGB) \ + do { \ + TCGv ireg = tcg_temp_new(); \ + TCGv tmp = tcg_temp_new(); \ + TCGv tmpV = tcg_temp_new(); \ + TCGv BYTE = tcg_temp_new(); \ + int i; \ + GET_EA; \ + fLOAD(1, 2, u, EA, tmpV); \ + tcg_gen_movi_tl(RdV, 0); \ + for (i = 0; i < 2; i++) { \ + fSETHALF(i, RdV, fGB(i, tmpV)); \ + } \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free(BYTE); \ + } while (0) + +#define fWRAP_L2_loadbzw2_io(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(fEA_RI(RsV, siV), fGETUBYTE) +#define fWRAP_L4_loadbzw2_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(fEA_IRs(UiV, RtV, uiV), fGETUBYTE) +#define fWRAP_L2_loadbsw2_io(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(fEA_RI(RsV, siV), fGETBYTE) +#define fWRAP_L4_loadbsw2_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(fEA_IRs(UiV, RtV, uiV), fGETBYTE) +#define fWRAP_L4_loadbzw2_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_ap, fGETUBYTE) +#define fWRAP_L2_loadbzw2_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pr, fGETUBYTE) +#define fWRAP_L2_loadbzw2_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pbr, fGETUBYTE) +#define fWRAP_L2_loadbzw2_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pi, fGETUBYTE) +#define fWRAP_L4_loadbsw2_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_ap, fGETBYTE) +#define fWRAP_L2_loadbsw2_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pr, fGETBYTE) +#define fWRAP_L2_loadbsw2_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pbr, fGETBYTE) +#define fWRAP_L2_loadbsw2_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pi, fGETBYTE) +#define fWRAP_L2_loadbzw2_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pci, fGETUBYTE) +#define fWRAP_L2_loadbsw2_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pci, fGETBYTE) +#define fWRAP_L2_loadbzw2_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pcr(1), fGETUBYTE) +#define fWRAP_L2_loadbsw2_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw2(GET_EA_pcr(1), fGETBYTE) + +/* + * These instructions load 4 bytes and places them in + * four halves of the destination register pair. + * The GET_EA macro determines the addressing mode. + * The fGB macro determines whether to zero-extend or + * sign-extend. + */ +#define fWRAP_loadbXw4(GET_EA, fGB) \ + do { \ + TCGv ireg = tcg_temp_new(); \ + TCGv tmp = tcg_temp_new(); \ + TCGv tmpV = tcg_temp_new(); \ + TCGv BYTE = tcg_temp_new(); \ + int i; \ + GET_EA; \ + fLOAD(1, 4, u, EA, tmpV); \ + tcg_gen_movi_i64(RddV, 0); \ + for (i = 0; i < 4; i++) { \ + fSETHALF(i, RddV, fGB(i, tmpV)); \ + } \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free(BYTE); \ + } while (0) + +#define fWRAP_L2_loadbzw4_io(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(fEA_RI(RsV, siV), fGETUBYTE) +#define fWRAP_L4_loadbzw4_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(fEA_IRs(UiV, RtV, uiV), fGETUBYTE) +#define fWRAP_L2_loadbsw4_io(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(fEA_RI(RsV, siV), fGETBYTE) +#define fWRAP_L4_loadbsw4_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(fEA_IRs(UiV, RtV, uiV), fGETBYTE) +#define fWRAP_L2_loadbzw4_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pci, fGETUBYTE) +#define fWRAP_L2_loadbsw4_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pci, fGETBYTE) +#define fWRAP_L2_loadbzw4_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pcr(2), fGETUBYTE) +#define fWRAP_L2_loadbsw4_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pcr(2), fGETBYTE) +#define fWRAP_L4_loadbzw4_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_ap, fGETUBYTE) +#define fWRAP_L2_loadbzw4_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pr, fGETUBYTE) +#define fWRAP_L2_loadbzw4_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pbr, fGETUBYTE) +#define fWRAP_L2_loadbzw4_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pi, fGETUBYTE) +#define fWRAP_L4_loadbsw4_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_ap, fGETBYTE) +#define fWRAP_L2_loadbsw4_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pr, fGETBYTE) +#define fWRAP_L2_loadbsw4_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pbr, fGETBYTE) +#define fWRAP_L2_loadbsw4_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadbXw4(GET_EA_pi, fGETBYTE) + +/* + * These instructions load a half word, shift the destination right by 16 bits + * and place the loaded value in the high half word of the destination pair. + * The GET_EA macro determines the addressing mode. + */ +#define fWRAP_loadalignh(GET_EA) \ + do { \ + TCGv ireg = tcg_temp_new(); \ + TCGv tmp = tcg_temp_new(); \ + TCGv tmpV = tcg_temp_new(); \ + TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ + READ_REG_PAIR(RyyV, RyyN); \ + GET_EA; \ + fLOAD(1, 2, u, EA, tmpV); \ + tcg_gen_extu_i32_i64(tmp_i64, tmpV); \ + tcg_gen_shli_i64(tmp_i64, tmp_i64, 48); \ + tcg_gen_shri_i64(RyyV, RyyV, 16); \ + tcg_gen_or_i64(RyyV, RyyV, tmp_i64); \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free_i64(tmp_i64); \ + } while (0) + +#define fWRAP_L4_loadalignh_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(fEA_IRs(UiV, RtV, uiV)) +#define fWRAP_L2_loadalignh_io(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(fEA_RI(RsV, siV)) +#define fWRAP_L2_loadalignh_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_pci) +#define fWRAP_L2_loadalignh_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_pcr(1)) +#define fWRAP_L4_loadalignh_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_ap) +#define fWRAP_L2_loadalignh_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_pr) +#define fWRAP_L2_loadalignh_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_pbr) +#define fWRAP_L2_loadalignh_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadalignh(GET_EA_pi) + +/* Same as above, but loads a byte instead of half word */ +#define fWRAP_loadalignb(GET_EA) \ + do { \ + TCGv ireg = tcg_temp_new(); \ + TCGv tmp = tcg_temp_new(); \ + TCGv tmpV = tcg_temp_new(); \ + TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ + READ_REG_PAIR(RyyV, RyyN); \ + GET_EA; \ + fLOAD(1, 1, u, EA, tmpV); \ + tcg_gen_extu_i32_i64(tmp_i64, tmpV); \ + tcg_gen_shli_i64(tmp_i64, tmp_i64, 56); \ + tcg_gen_shri_i64(RyyV, RyyV, 8); \ + tcg_gen_or_i64(RyyV, RyyV, tmp_i64); \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free_i64(tmp_i64); \ + } while (0) + +#define fWRAP_L2_loadalignb_io(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(fEA_RI(RsV, siV)) +#define fWRAP_L4_loadalignb_ur(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(fEA_IRs(UiV, RtV, uiV)) +#define fWRAP_L2_loadalignb_pci(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_pci) +#define fWRAP_L2_loadalignb_pcr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_pcr(0)) +#define fWRAP_L4_loadalignb_ap(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_ap) +#define fWRAP_L2_loadalignb_pr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_pr) +#define fWRAP_L2_loadalignb_pbr(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_pbr) +#define fWRAP_L2_loadalignb_pi(GENHLPR, SHORTCODE) \ + fWRAP_loadalignb(GET_EA_pi) + +#endif diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 5a602bd..6b9cc0d 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -26,6 +26,7 @@ #include "translate.h" #include "macros.h" #include "genptr_helpers.h" +#include "helper_overrides.h" #include "qemu_wrap_generated.h"

[RFC,v2,40/67] Hexagon TCG generation - step 02

Commit Message

Patch