From patchwork Fri Feb 28 16:43:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11413013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE75E138D for ; Fri, 28 Feb 2020 17:20:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91C4D246A2 for ; Fri, 28 Feb 2020 17:20:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="sLirLKZr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91C4D246A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jJT-00019s-Nj for patchwork-qemu-devel@patchwork.kernel.org; Fri, 28 Feb 2020 12:20:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58498) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7imD-0005lP-Tx for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7imA-0007JL-Nj for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:13 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:27035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7imA-0005Ug-B9 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908370; x=1614444370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dZMcL23+nYfUkbbRF6GyhrCSUY47Y4a40MuxhsRi4hk=; b=sLirLKZr+9BKseUfa30MGt2iJ84RW7CpEyUKxrZ74CpKNMCPD/3qeUdt mvjwFmYzMZbPGkSWVCa97bSIt+G5Wf0IncIDcHXTkxPCWE/SBCzR7OaqK BHybVgld4Ck+37dbf+Z2S8V/qv/PfxRButkjenF0WuuXgdcWeCA6MJu67 E=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 28 Feb 2020 08:44:34 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 28 Feb 2020 08:44:33 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id C4F83119A; Fri, 28 Feb 2020 10:44:33 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Date: Fri, 28 Feb 2020 10:43:58 -0600 Message-Id: <1582908244-304-63-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Various forms of declare, read, write, free for HVX operands Signed-off-by: Taylor Simpson --- target/hexagon/mmvec/macros.h | 262 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 262 insertions(+) create mode 100644 target/hexagon/mmvec/macros.h diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h new file mode 100644 index 0000000..be80bbd --- /dev/null +++ b/target/hexagon/mmvec/macros.h @@ -0,0 +1,262 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_MMVEC_MACROS_H +#define HEXAGON_MMVEC_MACROS_H + +#include "mmvec/system_ext_mmvec.h" + +#ifdef QEMU_GENERATE +#else +#define VdV (*(mmvector_t *)(VdV_void)) +#define VsV (*(mmvector_t *)(VsV_void)) +#define VuV (*(mmvector_t *)(VuV_void)) +#define VvV (*(mmvector_t *)(VvV_void)) +#define VwV (*(mmvector_t *)(VwV_void)) +#define VxV (*(mmvector_t *)(VxV_void)) +#define VyV (*(mmvector_t *)(VyV_void)) + +#define VddV (*(mmvector_pair_t *)(VddV_void)) +#define VuuV (*(mmvector_pair_t *)(VuuV_void)) +#define VvvV (*(mmvector_pair_t *)(VvvV_void)) +#define VxxV (*(mmvector_pair_t *)(VxxV_void)) + +#define QeV (*(mmqreg_t *)(QeV_void)) +#define QdV (*(mmqreg_t *)(QdV_void)) +#define QsV (*(mmqreg_t *)(QsV_void)) +#define QtV (*(mmqreg_t *)(QtV_void)) +#define QuV (*(mmqreg_t *)(QuV_void)) +#define QvV (*(mmqreg_t *)(QvV_void)) +#define QxV (*(mmqreg_t *)(QxV_void)) +#endif + +#ifdef QEMU_GENERATE +#define DECL_VREG(VAR, NUM, X, OFF) \ + TCGv_ptr VAR = tcg_temp_local_new_ptr(); \ + size1u_t NUM = REGNO(X) + OFF; \ + do { \ + uint32_t offset = new_temp_vreg_offset(ctx, 1); \ + tcg_gen_addi_ptr(VAR, cpu_env, offset); \ + } while (0) + +/* + * Certain instructions appear to have readonly operands, but + * in reality they do not. + * vdelta instructions overwrite their VuV operand + */ +static bool readonly_ok(insn_t *insn) +{ + uint32_t opcode = insn->opcode; + if (opcode == V6_vdelta || + opcode == V6_vrdelta) { + return false; + } + return true; +} + +#define DECL_VREG_READONLY(VAR, NUM, X, OFF) \ + TCGv_ptr VAR = tcg_temp_local_new_ptr(); \ + size1u_t NUM = REGNO(X) + OFF; \ + if (!readonly_ok(insn)) { \ + uint32_t offset = new_temp_vreg_offset(ctx, 1); \ + tcg_gen_addi_ptr(VAR, cpu_env, offset); \ + } + +#define DECL_VREG_d(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_s(VAR, NUM, X, OFF) \ + DECL_VREG_READONLY(VAR, NUM, X, OFF) +#define DECL_VREG_u(VAR, NUM, X, OFF) \ + DECL_VREG_READONLY(VAR, NUM, X, OFF) +#define DECL_VREG_v(VAR, NUM, X, OFF) \ + DECL_VREG_READONLY(VAR, NUM, X, OFF) +#define DECL_VREG_w(VAR, NUM, X, OFF) \ + DECL_VREG_READONLY(VAR, NUM, X, OFF) +#define DECL_VREG_x(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_y(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) + +#define DECL_VREG_PAIR(VAR, NUM, X, OFF) \ + TCGv_ptr VAR = tcg_temp_local_new_ptr(); \ + size1u_t NUM = REGNO(X) + OFF; \ + do { \ + uint32_t offset = new_temp_vreg_offset(ctx, 2); \ + tcg_gen_addi_ptr(VAR, cpu_env, offset); \ + } while (0) + +#define DECL_VREG_dd(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_uu(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_vv(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_xx(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) + +#define DECL_QREG(VAR, NUM, X, OFF) \ + TCGv_ptr VAR = tcg_temp_local_new_ptr(); \ + size1u_t NUM = REGNO(X) + OFF; \ + do { \ + uint32_t __offset = new_temp_qreg_offset(ctx); \ + tcg_gen_addi_ptr(VAR, cpu_env, __offset); \ + } while (0) + +#define DECL_QREG_d(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_e(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_s(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_t(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_u(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_v(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_x(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) + +#define FREE_VREG(VAR) tcg_temp_free_ptr(VAR) +#define FREE_VREG_d(VAR) FREE_VREG(VAR) +#define FREE_VREG_s(VAR) FREE_VREG(VAR) +#define FREE_VREG_u(VAR) FREE_VREG(VAR) +#define FREE_VREG_v(VAR) FREE_VREG(VAR) +#define FREE_VREG_w(VAR) FREE_VREG(VAR) +#define FREE_VREG_x(VAR) FREE_VREG(VAR) +#define FREE_VREG_y(VAR) FREE_VREG(VAR) + +#define FREE_VREG_PAIR(VAR) tcg_temp_free_ptr(VAR) +#define FREE_VREG_dd(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_uu(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_vv(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_xx(VAR) FREE_VREG_PAIR(VAR) + +#define FREE_QREG(VAR) tcg_temp_free_ptr(VAR) +#define FREE_QREG_d(VAR) FREE_QREG(VAR) +#define FREE_QREG_e(VAR) FREE_QREG(VAR) +#define FREE_QREG_s(VAR) FREE_QREG(VAR) +#define FREE_QREG_t(VAR) FREE_QREG(VAR) +#define FREE_QREG_u(VAR) FREE_QREG(VAR) +#define FREE_QREG_v(VAR) FREE_QREG(VAR) +#define FREE_QREG_x(VAR) FREE_QREG(VAR) + +#define READ_VREG(VAR, NUM) \ + gen_read_vreg(VAR, NUM, 0) +#define READ_VREG_READONLY(VAR, NUM) \ + do { \ + if (readonly_ok(insn)) { \ + gen_read_vreg_readonly(VAR, NUM, 0); \ + } else { \ + gen_read_vreg(VAR, NUM, 0); \ + } \ + } while (0) + +#define READ_VREG_s(VAR, NUM) READ_VREG_READONLY(VAR, NUM) +#define READ_VREG_u(VAR, NUM) READ_VREG_READONLY(VAR, NUM) +#define READ_VREG_v(VAR, NUM) READ_VREG_READONLY(VAR, NUM) +#define READ_VREG_w(VAR, NUM) READ_VREG_READONLY(VAR, NUM) +#define READ_VREG_x(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_y(VAR, NUM) READ_VREG(VAR, NUM) + +#define READ_VREG_PAIR(VAR, NUM) \ + gen_read_vreg_pair(VAR, NUM, 0) +#define READ_VREG_uu(VAR, NUM) READ_VREG_PAIR(VAR, NUM) +#define READ_VREG_vv(VAR, NUM) READ_VREG_PAIR(VAR, NUM) +#define READ_VREG_xx(VAR, NUM) READ_VREG_PAIR(VAR, NUM) + +#define READ_QREG(VAR, NUM) \ + gen_read_qreg(VAR, NUM, 0) +#define READ_QREG_s(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_t(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_u(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_v(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_x(VAR, NUM) READ_QREG(VAR, NUM) + +#define DECL_NEW_OREG(TYPE, NAME, NUM, X, OFF) \ + TYPE NAME; \ + int NUM = REGNO(X) + OFF + +#define READ_NEW_OREG(tmp, i) (tmp = tcg_const_tl(i)) + +#define FREE_NEW_OREG(NAME) \ + tcg_temp_free(NAME) + +#define LOG_VREG_WRITE(NUM, VAR, VNEW) \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_vreg_write(VAR, NUM, VNEW, insn->slot); \ + ctx_log_vreg_write(ctx, (NUM), is_predicated); \ + } while (0) + +#define LOG_VREG_WRITE_PAIR(NUM, VAR, VNEW) \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_vreg_write_pair(VAR, NUM, VNEW, insn->slot); \ + ctx_log_vreg_write(ctx, (NUM) ^ 0, is_predicated); \ + ctx_log_vreg_write(ctx, (NUM) ^ 1, is_predicated); \ + } while (0) + +#define LOG_QREG_WRITE(NUM, VAR, VNEW) \ + do { \ + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_qreg_write(VAR, NUM, VNEW, insn->slot); \ + ctx_log_qreg_write(ctx, (NUM), is_predicated); \ + } while (0) +#else +#define NEW_WRITTEN(NUM) ((env->VRegs_select >> (NUM)) & 1) +#define TMP_WRITTEN(NUM) ((env->VRegs_updated_tmp >> (NUM)) & 1) + +#define LOG_VREG_WRITE_FUNC(X) \ + _Generic((X), void * : log_vreg_write, mmvector_t : log_mmvector_write) +#define LOG_VREG_WRITE(NUM, VAR, VNEW) \ + LOG_VREG_WRITE_FUNC(VAR)(env, NUM, VAR, VNEW, slot) + +#define READ_EXT_VREG(NUM, VAR, VTMP) \ + do { \ + VAR = ((NEW_WRITTEN(NUM)) ? env->future_VRegs[NUM] \ + : env->VRegs[NUM]); \ + VAR = ((TMP_WRITTEN(NUM)) ? env->tmp_VRegs[NUM] : VAR); \ + if (VTMP == EXT_TMP) { \ + if (env->VRegs_updated & ((VRegMask)1) << (NUM)) { \ + VAR = env->future_VRegs[NUM]; \ + env->VRegs_updated ^= ((VRegMask)1) << (NUM); \ + } \ + } \ + } while (0) + +#define READ_EXT_VREG_PAIR(NUM, VAR, VTMP) \ + do { \ + READ_EXT_VREG((NUM) ^ 0, VAR.v[0], VTMP); \ + READ_EXT_VREG((NUM) ^ 1, VAR.v[1], VTMP) \ + } while (0) +#endif + +#define WRITE_EXT_VREG(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_d(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_x(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_y(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) + +#define WRITE_VREG_dd(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNEW) +#define WRITE_VREG_xx(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNEW) +#define WRITE_VREG_yy(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNEW) + +#define WRITE_QREG_d(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) +#define WRITE_QREG_e(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) +#define WRITE_QREG_x(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) + +#endif