From patchwork Fri Feb 28 16:44:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11413029 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC0E813A4 for ; Fri, 28 Feb 2020 17:22:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3D75246A0 for ; Fri, 28 Feb 2020 17:22:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="f/FCuev9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3D75246A0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jLS-00051L-SK for patchwork-qemu-devel@patchwork.kernel.org; Fri, 28 Feb 2020 12:22:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58778) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7iml-0006R5-Sj for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7imk-0008SH-K1 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:47 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:13235) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7imk-0005U6-Bj for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908406; x=1614444406; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5dtSBjj52Ssvq6HI1Wg5nGX10+YCefffGSRX4qMo3/c=; b=f/FCuev9XTrDAn+3BXxp2L/737yzR1rtMzBr4to/QXhWn2o/U8szaTsm RKCj9g7IkSxFU+59FOoklEf66cZAnv3O8O7rRsx5iJj4hSKfmVe/f++HU 2CmyzBV3r83BPIBcfoLDrg468t+oi6lOnA1AJXKvj2dwglxtGo01OFSkl k=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Feb 2020 08:44:35 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 28 Feb 2020 08:44:34 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id F31EA1110; Fri, 28 Feb 2020 10:44:33 -0600 (CST) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Date: Fri, 28 Feb 2020 10:44:00 -0600 Message-Id: <1582908244-304-65-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.38 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 1 + target/hexagon/op_helper.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 8558da8..64e798b 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(debug_start_packet, void, env) DEF_HELPER_2(new_value, s32, env, int) DEF_HELPER_3(debug_check_store_width, void, env, int, int) +DEF_HELPER_1(commit_hvx_stores, void, env) DEF_HELPER_3(debug_commit_end, void, env, int, int) DEF_HELPER_3(sfrecipa_val, s32, env, s32, s32) DEF_HELPER_3(sfrecipa_pred, s32, env, s32, s32) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index d944d03..72250cc 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -26,6 +26,8 @@ #include "arch.h" #include "fma_emu.h" #include "conv_emu.h" +#include "mmvec/mmvec.h" +#include "mmvec/macros.h" #if COUNT_HEX_HELPERS #include "opcodes.h" @@ -199,6 +201,51 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) } } +void HELPER(commit_hvx_stores)(CPUHexagonState *env) +{ + int i; + + /* Normal (possibly masked) vector store */ + for (i = 0; i < VSTORES_MAX; i++) { + if (env->vstore_pending[i]) { + env->vstore_pending[i] = 0; + target_ulong va = env->vstore[i].va; + int size = env->vstore[i].size; + for (int j = 0; j < size; j++) { + if (env->vstore[i].mask.ub[j]) { + put_user_u8(env->vstore[i].data.ub[j], va + j); + } + } + } + } + + /* Scatter store */ + if (env->vtcm_pending) { + env->vtcm_pending = 0; + if (env->vtcm_log.op) { + /* Need to perform the scatter read/modify/write at commit time */ + if (env->vtcm_log.op_size == 2) { + SCATTER_OP_WRITE_TO_MEM(size2u_t); + } else if (env->vtcm_log.op_size == 4) { + /* Word Scatter += */ + SCATTER_OP_WRITE_TO_MEM(size4u_t); + } else { + g_assert_not_reached(); + } + } else { + for (int i = 0; i < env->vtcm_log.size; i++) { + if (env->vtcm_log.mask.ub[i] != 0) { + put_user_u8(env->vtcm_log.data.ub[i], env->vtcm_log.va[i]); + env->vtcm_log.mask.ub[i] = 0; + env->vtcm_log.data.ub[i] = 0; + env->vtcm_log.offsets.ub[i] = 0; + } + + } + } + } +} + static void print_store(CPUHexagonState *env, int slot) { if (!(env->slot_cancelled & (1 << slot))) { @@ -415,6 +462,34 @@ void HELPER(debug_value_i64)(CPUHexagonState *env, int64_t value) HEX_DEBUG_LOG("value = 0x%lx\n", value); } +/* Log a write to HVX vector */ +static inline void log_vreg_write(CPUHexagonState *env, int num, void *var, + int vnew, uint32_t slot) +{ + HEX_DEBUG_LOG("log_vreg_write[%d]", num); + if (env->slot_cancelled & (1 << slot)) { + HEX_DEBUG_LOG(" CANCELLED"); + } + HEX_DEBUG_LOG("\n"); + + if (!(env->slot_cancelled & (1 << slot))) { + VRegMask regnum_mask = ((VRegMask)1) << num; + env->VRegs_updated |= (vnew != EXT_TMP) ? regnum_mask : 0; + env->VRegs_select |= (vnew == EXT_NEW) ? regnum_mask : 0; + env->VRegs_updated_tmp |= (vnew == EXT_TMP) ? regnum_mask : 0; + env->future_VRegs[num] = *(mmvector_t *)var; + if (vnew == EXT_TMP) { + env->tmp_VRegs[num] = env->future_VRegs[num]; + } + } +} + +static inline void log_mmvector_write(CPUHexagonState *env, int num, + mmvector_t var, int vnew, uint32_t slot) +{ + log_vreg_write(env, num, &var, vnew, slot); +} + static void cancel_slot(CPUHexagonState *env, uint32_t slot) { HEX_DEBUG_LOG("Slot %d cancelled\n", slot);