From patchwork Sun Mar 22 12:36:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Liu X-Patchwork-Id: 11451755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F9E16CA for ; Sun, 22 Mar 2020 12:35:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F16E206F8 for ; Sun, 22 Mar 2020 12:35:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7F16E206F8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFzpb-0001Iv-JW for patchwork-qemu-devel@patchwork.kernel.org; Sun, 22 Mar 2020 08:35:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47899) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFzkn-0000xh-Js for qemu-devel@nongnu.org; Sun, 22 Mar 2020 08:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jFzkk-0003t1-H5 for qemu-devel@nongnu.org; Sun, 22 Mar 2020 08:30:57 -0400 Received: from mga02.intel.com ([134.134.136.20]:41735) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jFzkf-0003ol-7u for qemu-devel@nongnu.org; Sun, 22 Mar 2020 08:30:51 -0400 IronPort-SDR: 3LNoZZu41vdHmNlUZHlHU3OthoOgYe29fOiUSrmXzME3zUYFxo3ZvV11uH+YLYXMxB6ivLZg6q bNHMmcgG2nIw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2020 05:30:38 -0700 IronPort-SDR: MxBsRZpx6VRupLILemblATcZ9jcMl5h/e5k69U5TYb82YM3CXXWkyBesqDNa9eMYVyPIgVOEeU LNVN+9t9c1eQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,292,1580803200"; d="scan'208";a="239664370" Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by orsmga008.jf.intel.com with ESMTP; 22 Mar 2020 05:30:38 -0700 From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [PATCH v1 07/22] intel_iommu: add set/unset_iommu_context callback Date: Sun, 22 Mar 2020 05:36:04 -0700 Message-Id: <1584880579-12178-8-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584880579-12178-1-git-send-email-yi.l.liu@intel.com> References: <1584880579-12178-1-git-send-email-yi.l.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.20 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , Eduardo Habkost , kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , pbonzini@redhat.com, hao.wu@intel.com, Richard Henderson , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch adds set/unset_iommu_context() impelementation in Intel vIOMMU. For Intel platform, pass-through modules (e.g. VFIO) could set HostIOMMUContext to Intel vIOMMU emulator. Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Liu Yi L --- hw/i386/intel_iommu.c | 70 +++++++++++++++++++++++++++++++++++++++---- include/hw/i386/intel_iommu.h | 17 +++++++++-- 2 files changed, 80 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4b22910..8d9204f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3354,23 +3354,35 @@ static const MemoryRegionOps vtd_mem_ir_ops = { }, }; -VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) +/** + * Fetch a VTDBus instance for given PCIBus. If no existing instance, + * allocate one. + */ +static VTDBus *vtd_find_add_bus(IntelIOMMUState *s, PCIBus *bus) { uintptr_t key = (uintptr_t)bus; VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key); - VTDAddressSpace *vtd_dev_as; - char name[128]; if (!vtd_bus) { uintptr_t *new_key = g_malloc(sizeof(*new_key)); *new_key = (uintptr_t)bus; /* No corresponding free() */ - vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \ - PCI_DEVFN_MAX); + vtd_bus = g_malloc0(sizeof(VTDBus) + PCI_DEVFN_MAX * \ + (sizeof(VTDAddressSpace *) + \ + sizeof(VTDHostIOMMUContext *))); vtd_bus->bus = bus; g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); } + return vtd_bus; +} + +VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) +{ + VTDBus *vtd_bus; + VTDAddressSpace *vtd_dev_as; + char name[128]; + vtd_bus = vtd_find_add_bus(s, bus); vtd_dev_as = vtd_bus->dev_as[devfn]; if (!vtd_dev_as) { @@ -3436,6 +3448,52 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) return vtd_dev_as; } +static int vtd_dev_set_iommu_context(PCIBus *bus, void *opaque, + int devfn, + HostIOMMUContext *host_icx) +{ + IntelIOMMUState *s = opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <= devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus = vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + vtd_dev_icx = vtd_bus->dev_icx[devfn]; + + if (!vtd_dev_icx) { + vtd_bus->dev_icx[devfn] = vtd_dev_icx = + g_malloc0(sizeof(VTDHostIOMMUContext)); + vtd_dev_icx->vtd_bus = vtd_bus; + vtd_dev_icx->devfn = (uint8_t)devfn; + vtd_dev_icx->iommu_state = s; + vtd_dev_icx->host_icx = host_icx; + } + vtd_iommu_unlock(s); + + return 0; +} + +static void vtd_dev_unset_iommu_context(PCIBus *bus, void *opaque, int devfn) +{ + IntelIOMMUState *s = opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <= devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus = vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + + vtd_dev_icx = vtd_bus->dev_icx[devfn]; + g_free(vtd_dev_icx); + + vtd_iommu_unlock(s); +} + static uint64_t get_naturally_aligned_size(uint64_t start, uint64_t size, int gaw) { @@ -3731,6 +3789,8 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) static PCIIOMMUOps vtd_iommu_ops = { .get_address_space = vtd_host_dma_iommu, + .set_iommu_context = vtd_dev_set_iommu_context, + .unset_iommu_context = vtd_dev_unset_iommu_context, }; static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 3870052..9b4fc0a 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -64,6 +64,7 @@ typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; typedef struct VTDPASIDEntry VTDPASIDEntry; +typedef struct VTDHostIOMMUContext VTDHostIOMMUContext; /* Context-Entry */ struct VTDContextEntry { @@ -112,10 +113,20 @@ struct VTDAddressSpace { IOVATree *iova_tree; /* Traces mapped IOVA ranges */ }; +struct VTDHostIOMMUContext { + VTDBus *vtd_bus; + uint8_t devfn; + HostIOMMUContext *host_icx; + IntelIOMMUState *iommu_state; +}; + struct VTDBus { - PCIBus* bus; /* A reference to the bus to provide translation for */ + /* A reference to the bus to provide translation for */ + PCIBus *bus; /* A table of VTDAddressSpace objects indexed by devfn */ - VTDAddressSpace *dev_as[]; + VTDAddressSpace *dev_as[PCI_DEVFN_MAX]; + /* A table of VTDHostIOMMUContext objects indexed by devfn */ + VTDHostIOMMUContext *dev_icx[PCI_DEVFN_MAX]; }; struct VTDIOTLBEntry { @@ -271,6 +282,8 @@ struct IntelIOMMUState { /* * Protects IOMMU states in general. Currently it protects the * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. + * Protect the update/usage of HostIOMMUContext pointer cached in + * VTDBus->dev_icx array as array elements may be updated by hotplug */ QemuMutex iommu_lock; };