| Message ID | 1589393329-223076-4-git-send-email-komlodi@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V2,1/4] target/microblaze: gdb: Add dynamic GDB XML register support | expand |
On Wed, May 13, 2020 at 11:08:48AM -0700, Joe Komlodi wrote: > Increase the number of registers reported to match GDB. > > Registers that aren't modeled are reported as 0. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > target/microblaze/translate.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 20b7427..4e7f903a 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -1788,9 +1788,11 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) > qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", > env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); > qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " > - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", > + "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " > + "rbtr=%" PRIx64 "\n", > env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], > - env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); > + env->debug, env->imm, env->iflags, env->sregs[SR_FSR], > + env->sregs[SR_BTR]); > qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " > "eip=%d ie=%d\n", > env->btaken, env->btarget, > @@ -1798,7 +1800,17 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) > (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", > (bool)(env->sregs[SR_MSR] & MSR_EIP), > (bool)(env->sregs[SR_MSR] & MSR_IE)); > + for (i = 0; i < 12; i++) { > + qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); > + if ((i + 1) % 4 == 0) { > + qemu_fprintf(f, "\n"); > + } > + } > > + /* Registers that aren't modeled are reported as 0 */ > + qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " > + "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); > + qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); > for (i = 0; i < 32; i++) { > qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); > if ((i + 1) % 4 == 0) > -- > 2.7.4 >
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 20b7427..4e7f903a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1788,9 +1788,11 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "rbtr=%" PRIx64 "\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], - env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); + env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " "eip=%d ie=%d\n", env->btaken, env->btarget, @@ -1798,7 +1800,17 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", (bool)(env->sregs[SR_MSR] & MSR_EIP), (bool)(env->sregs[SR_MSR] & MSR_IE)); + for (i = 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); + if ((i + 1) % 4 == 0) { + qemu_fprintf(f, "\n"); + } + } + /* Registers that aren't modeled are reported as 0 */ + qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " + "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0)
Increase the number of registers reported to match GDB. Registers that aren't modeled are reported as 0. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> --- target/microblaze/translate.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)