From patchwork Tue Aug 18 15:50:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11721875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B05EE1392 for ; Tue, 18 Aug 2020 15:58:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8637520888 for ; Tue, 18 Aug 2020 15:58:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ex8/fpHT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8637520888 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:34428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k840l-0004WM-PB for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Aug 2020 11:58:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tF-0006VN-8y for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:09 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:12936) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tC-0005rl-59 for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765866; x=1629301866; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ux1k5hYF9qLQLllMcTqCoD+cbXI4RSKWLJ81WLxqDvs=; b=ex8/fpHTgBEH1zLJwndsQqPbt8p48G3bdRE37c7BtNQozpZf5pJrUh9l jHiN8DfuD5y7CdntMKTTSYkFyJa7EEd9GiQ3mtg3d/vZTqnevlBiaA8TO JMs/aZ8Less3JN0K3npfavwHyYAOhg7fOYMXFXpP5PZwIrbfsTdb88Jzo M=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:50:57 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 3E075848; Tue, 18 Aug 2020 10:50:56 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 11/34] Hexagon (target/hexagon) register fields Date: Tue, 18 Aug 2020 10:50:24 -0500 Message-Id: <1597765847-16637-12-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.h | 40 +++++++++++++++++++++ target/hexagon/reg_fields_def.h | 78 +++++++++++++++++++++++++++++++++++++++++ target/hexagon/reg_fields.c | 28 +++++++++++++++ 3 files changed, 146 insertions(+) create mode 100644 target/hexagon/reg_fields.h create mode 100644 target/hexagon/reg_fields_def.h create mode 100644 target/hexagon/reg_fields.c diff --git a/target/hexagon/reg_fields.h b/target/hexagon/reg_fields.h new file mode 100644 index 0000000..cf168f0 --- /dev/null +++ b/target/hexagon/reg_fields.h @@ -0,0 +1,40 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_REG_FIELDS_H +#define HEXAGON_REG_FIELDS_H + +#define NUM_GEN_REGS 32 + +typedef struct { + const char *name; + int offset; + int width; + const char *description; +} reg_field_t; + +extern reg_field_t reg_field_info[]; + +enum reg_fields_enum { +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ + TAG, +#include "reg_fields_def.h" + NUM_REG_FIELDS +#undef DEF_REG_FIELD +}; + +#endif diff --git a/target/hexagon/reg_fields_def.h b/target/hexagon/reg_fields_def.h new file mode 100644 index 0000000..ffb18a1 --- /dev/null +++ b/target/hexagon/reg_fields_def.h @@ -0,0 +1,78 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * For registers that have individual fields, explain them here + * DEF_REG_FIELD(tag, + * name, + * bit start offset, + * width, + * description + */ + +/* USR fields */ +DEF_REG_FIELD(USR_OVF, + "ovf", 0, 1, + "Sticky Saturation Overflow - " + "Set when saturation occurs while executing instruction that specifies " + "optional saturation, remains set until explicitly cleared by a USR=Rs " + "instruction.") +DEF_REG_FIELD(USR_FPINVF, + "fpinvf", 1, 1, + "Floating-point IEEE Invalid Sticky Flag.") +DEF_REG_FIELD(USR_FPDBZF, + "fpdbzf", 2, 1, + "Floating-point IEEE Divide-By-Zero Sticky Flag.") +DEF_REG_FIELD(USR_FPOVFF, + "fpovff", 3, 1, + "Floating-point IEEE Overflow Sticky Flag.") +DEF_REG_FIELD(USR_FPUNFF, + "fpunff", 4, 1, + "Floating-point IEEE Underflow Sticky Flag.") +DEF_REG_FIELD(USR_FPINPF, + "fpinpf", 5, 1, + "Floating-point IEEE Inexact Sticky Flag.") + +DEF_REG_FIELD(USR_LPCFG, + "lpcfg", 8, 2, + "Hardware Loop Configuration: " + "Number of loop iterations (0-3) remaining before pipeline predicate " + "should be set.") + +DEF_REG_FIELD(USR_FPRND, + "fprnd", 22, 2, + "Rounding Mode for Floating-Point Instructions: " + "00: Round to nearest, ties to even (default), " + "01: Toward zero, " + "10: Downward (toward negative infinity), " + "11: Upward (toward positive infinity).") + +DEF_REG_FIELD(USR_FPINVE, + "fpinve", 25, 1, + "Enable trap on IEEE Invalid.") +DEF_REG_FIELD(USR_FPDBZE, + "fpdbze", 26, 1, "Enable trap on IEEE Divide-By-Zero.") +DEF_REG_FIELD(USR_FPOVFE, + "fpovfe", 27, 1, + "Enable trap on IEEE Overflow.") +DEF_REG_FIELD(USR_FPUNFE, + "fpunfe", 28, 1, + "Enable trap on IEEE Underflow.") +DEF_REG_FIELD(USR_FPINPE, + "fpinpe", 29, 1, + "Enable trap on IEEE Inexact.") + diff --git a/target/hexagon/reg_fields.c b/target/hexagon/reg_fields.c new file mode 100644 index 0000000..2a3e4f5a --- /dev/null +++ b/target/hexagon/reg_fields.c @@ -0,0 +1,28 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "reg_fields.h" + +reg_field_t reg_field_info[] = { +#define DEF_REG_FIELD(TAG, NAME, START, WIDTH, DESCRIPTION) \ + {NAME, START, WIDTH, DESCRIPTION}, +#include "reg_fields_def.h" + {NULL, 0, 0} +#undef DEF_REG_FIELD +}; +