From patchwork Tue Aug 18 15:50:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11721917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59D05722 for ; Tue, 18 Aug 2020 16:04:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3020D20639 for ; Tue, 18 Aug 2020 16:04:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EbXLUWFk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3020D20639 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k846V-0006SY-Bt for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Aug 2020 12:04:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tm-0007nC-QZ for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:44 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:12947) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tj-0005sa-Cn for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765899; x=1629301899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w6tiKpk4csTikjQRQqrcLl3i8YzkM8G9GGhrIgGFbQU=; b=EbXLUWFk3TwfQMuJnk9sgiG2jO13k3qH1sYXZ9pQ99Rv/XvmpkeILIdR 5zb1A6itdRgQT6KfkbEZ5cnolacnkSM3TEV4SWrAUUfqsv5CPi13bQwDm zWBBOm+x41KzHazXtkXpaLij8nnm2kwalIhI1tAk06gkZSaOEFu5ZtyFh 8=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:57 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 9B1AB8F7; Tue, 18 Aug 2020 10:50:57 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 20/34] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Date: Tue, 18 Aug 2020 10:50:33 -0500 Message-Id: <1597765847-16637-21-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:50:57 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Run the C preprocessor across the instruction definition files and macro definitoin file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson --- target/hexagon/gen_semantics.c | 88 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 target/hexagon/gen_semantics.c diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantics.c new file mode 100644 index 0000000..1b198cb --- /dev/null +++ b/target/hexagon/gen_semantics.c @@ -0,0 +1,88 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * This program generates the semantics file that is processed by + * the do_qemu.py script. We use the C preporcessor to manipulate the + * files imported from the Hexagon architecture library. + */ + +#include +#define STRINGIZE(X) #X + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); + return -1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return -1; + } + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + */ +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + do { \ + fprintf(outfile, "SEMANTICS( \\\n" \ + " \"%s\", \\\n" \ + " %s, \\\n" \ + " \"\"\"%s\"\"\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ + fprintf(outfile, "ATTRIBUTES( \\\n" \ + " \"%s\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(ATTRIBS)); \ + } while (0); +#include "imported/allidefs.def" +#undef Q6INSN + +/* + * Process the macro definitions + * Macros definitions have the following form + * DEF_MACRO( + * fLSBNEW0, + * predlog_read(thread,0), + * () + * ) + * The important part here is the attributes. Whenever an instruction + * invokes a macro, we add the macro's attributes to the instruction. + */ +#define DEF_MACRO(MNAME, BEH, ATTRS) \ + fprintf(outfile, "MACROATTRIB( \\\n" \ + " \"%s\", \\\n" \ + " \"\"\"%s\"\"\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); +#include "imported/macros.def" +#undef DEF_MACRO + + fclose(outfile); + return 0; +}