From patchwork Tue Aug 18 15:50:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11721933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50C1E14F6 for ; Tue, 18 Aug 2020 16:07:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 184C22076E for ; Tue, 18 Aug 2020 16:07:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="zpGIxdXR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 184C22076E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:39620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k849S-0002X2-9b for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Aug 2020 12:07:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tL-0006iX-8S for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:15 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:55147) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tH-0005r3-2y for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765871; x=1629301871; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZP82MTfYnmOflHHB8pyYBGXkzdx6M6wBBtL8qISwEto=; b=zpGIxdXRTzivNTgeI+J2LDxkH3++nvnxVNOUa94jfy1njf4xpBd3k7LA AFtCXFEusom89M7nLaXqZCtyveWmFlSUeFmhPSpBT3iHUHkluVYb3b+vX qBRoBCXuCphj6HtoYExnpID5HhPyGmQlrJQ4EbJCAQoc7aWBobGd+5IN6 U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 Aug 2020 08:50:58 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D30E317F5; Tue, 18 Aug 2020 10:50:55 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 07/34] Hexagon (target/hexagon) scalar core helpers Date: Tue, 18 Aug 2020 10:50:20 -0500 Message-Id: <1597765847-16637-8-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 33 ++++ target/hexagon/op_helper.c | 368 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 401 insertions(+) create mode 100644 target/hexagon/helper.h create mode 100644 target/hexagon/op_helper.c diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h new file mode 100644 index 0000000..48b1917 --- /dev/null +++ b/target/hexagon/helper.h @@ -0,0 +1,33 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_1(debug_start_packet, void, env) +DEF_HELPER_3(debug_check_store_width, void, env, int, int) +DEF_HELPER_3(debug_commit_end, void, env, int, int) +DEF_HELPER_3(merge_inflight_store1s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store1u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store2s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store2u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store4s, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store4u, s32, env, s32, s32) +DEF_HELPER_3(merge_inflight_store8u, s64, env, s32, s64) + +#include "helper_protos_generated.h" + +DEF_HELPER_2(debug_value, void, env, s32) +DEF_HELPER_2(debug_value_i64, void, env, s64) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c new file mode 100644 index 0000000..f86d45b --- /dev/null +++ b/target/hexagon/op_helper.c @@ -0,0 +1,368 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include "qemu/osdep.h" +#include "qemu.h" +#include "exec/helper-proto.h" +#include "cpu.h" +#include "internal.h" +#include "macros.h" +#include "arch.h" +#include "fma_emu.h" +#include "conv_emu.h" + +/* Exceptions processing helpers */ +static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env, + uint32_t exception, + uintptr_t pc) +{ + CPUState *cs = CPU(hexagon_env_get_cpu(env)); + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); + cs->exception_index = exception; + cpu_loop_exit_restore(cs, pc); +} + +void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exception) +{ + do_raise_exception_err(env, exception, 0); +} + +static inline void log_reg_write(CPUHexagonState *env, int rnum, + target_ulong val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")", + rnum, val, val); + if (env->slot_cancelled & (1 << slot)) { + HEX_DEBUG_LOG(" CANCELLED"); + } + if (val == env->gpr[rnum]) { + HEX_DEBUG_LOG(" NO CHANGE"); + } + HEX_DEBUG_LOG("\n"); + if (!(env->slot_cancelled & (1 << slot))) { + env->new_value[rnum] = val; +#if HEX_DEBUG + /* Do this so HELPER(debug_commit_end) will know */ + env->reg_written[rnum] = 1; +#endif + } +} + +static __attribute__((unused)) +inline void log_reg_write_pair(CPUHexagonState *env, int rnum, + int64_t val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val); + log_reg_write(env, rnum, val & 0xFFFFFFFF, slot); + log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot); +} + +static inline void log_pred_write(CPUHexagonState *env, int pnum, + target_ulong val) +{ + HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld + " (0x" TARGET_FMT_lx ")\n", + pnum, val, val); + + /* Multiple writes to the same preg are and'ed together */ + if (env->pred_written & (1 << pnum)) { + env->new_pred_value[pnum] &= val & 0xff; + } else { + env->new_pred_value[pnum] = val & 0xff; + env->pred_written |= 1 << pnum; + } +} + +static inline void log_store32(CPUHexagonState *env, target_ulong addr, + target_ulong val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld + " [0x" TARGET_FMT_lx "])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data32 = val; +} + +static inline void log_store64(CPUHexagonState *env, target_ulong addr, + int64_t val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data64 = val; +} + +static inline void write_new_pc(CPUHexagonState *env, target_ulong addr) +{ + HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); + + /* + * If more than one branch is taken in a packet, only the first one + * is actually done. + */ + if (env->branch_taken) { + HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " + "ignoring the second one\n"); + } else { + fCHECK_PCALIGN(addr); + env->branch_taken = 1; + env->next_PC = addr; + } +} + +/* Handy place to set a breakpoint */ +void HELPER(debug_start_packet)(CPUHexagonState *env) +{ + HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", + env->gpr[HEX_REG_PC]); + + int i; + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + env->reg_written[i] = 0; + } +} + +static inline int32_t new_pred_value(CPUHexagonState *env, int pnum) +{ + return env->new_pred_value[pnum]; +} + +/* Checks for bookkeeping errors between disassembly context and runtime */ +void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) +{ + if (env->mem_log_stores[slot].width != check) { + HEX_DEBUG_LOG("ERROR: %d != %d\n", + env->mem_log_stores[slot].width, check); + g_assert_not_reached(); + } +} + +static void print_store(CPUHexagonState *env, int slot) +{ + if (!(env->slot_cancelled & (1 << slot))) { + size1u_t width = env->mem_log_stores[slot].width; + if (width == 1) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xff; + HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %d (0x%02x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 2) { + size4u_t data = env->mem_log_stores[slot].data32 & 0xffff; + HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %d (0x%04x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 4) { + size4u_t data = env->mem_log_stores[slot].data32; + HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %d (0x%08x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 8) { + HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu (0x%016lx)\n", + env->mem_log_stores[slot].va, + env->mem_log_stores[slot].data64, + env->mem_log_stores[slot].data64); + } else { + HEX_DEBUG_LOG("\tBad store width %d\n", width); + g_assert_not_reached(); + } + } +} + +/* This function is a handy place to set a breakpoint */ +void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) +{ + bool reg_printed = false; + bool pred_printed = false; + int i; + + HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", + env->this_PC); + HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled); + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + if (env->reg_written[i]) { + if (!reg_printed) { + HEX_DEBUG_LOG("Regs written\n"); + reg_printed = true; + } + HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", + i, env->new_value[i], env->new_value[i]); + } + } + + for (i = 0; i < NUM_PREGS; i++) { + if (env->pred_written & (1 << i)) { + if (!pred_printed) { + HEX_DEBUG_LOG("Predicates written\n"); + pred_printed = true; + } + HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", + i, env->new_pred_value[i]); + } + } + + if (has_st0 || has_st1) { + HEX_DEBUG_LOG("Stores\n"); + if (has_st0) { + print_store(env, 0); + } + if (has_st1) { + print_store(env, 1); + } + } + + HEX_DEBUG_LOG("Next PC = 0x%x\n", env->next_PC); + HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx + ", insn = " TARGET_FMT_lx + "\n", + env->gpr[HEX_REG_QEMU_PKT_CNT], + env->gpr[HEX_REG_QEMU_INSN_CNT]); + +} + +/* + * Handle mem_noshuf + * + * This occurs when there is a load that might need data forwarded + * from an inflight store in slot 1. Note that the load and store + * might have different sizes, so we can't simply compare the + * addresses. We merge only the bytes that overlap (if any). + */ +static int64_t merge_bytes(CPUHexagonState *env, target_ulong load_addr, + int64_t load_data, uint32_t load_width) +{ + /* Don't do anything if slot 1 was cancelled */ + const int store_slot = 1; + if (env->slot_cancelled & (1 << store_slot)) { + return load_data; + } + + int store_width = env->mem_log_stores[store_slot].width; + target_ulong store_addr = env->mem_log_stores[store_slot].va; + union { + uint8_t bytes[8]; + uint32_t data32; + uint64_t data64; + } retdata, storedata; + int bigmask = ((-load_width) & (-store_width)); + if ((load_addr & bigmask) != (store_addr & bigmask)) { + /* no overlap */ + return load_data; + } + retdata.data64 = load_data; + + if (store_width == 1 || store_width == 2 || store_width == 4) { + storedata.data32 = env->mem_log_stores[store_slot].data32; + } else if (store_width == 8) { + storedata.data64 = env->mem_log_stores[store_slot].data64; + } else { + g_assert_not_reached(); + } + int i, j; + i = store_addr & (load_width - 1); + j = load_addr & (store_width - 1); + while ((i < load_width) && (j < store_width)) { + retdata.bytes[i] = storedata.bytes[j]; + i++; + j++; + } + return retdata.data64; +} + +#define MERGE_INFLIGHT(NAME, RET, IN_TYPE, OUT_TYPE, SIZE) \ +RET HELPER(NAME)(CPUHexagonState *env, int32_t addr, IN_TYPE data) \ +{ \ + return (OUT_TYPE)merge_bytes(env, addr, data, SIZE); \ +} + +MERGE_INFLIGHT(merge_inflight_store1s, int32_t, int32_t, int8_t, 1) +MERGE_INFLIGHT(merge_inflight_store1u, int32_t, int32_t, uint8_t, 1) +MERGE_INFLIGHT(merge_inflight_store2s, int32_t, int32_t, int16_t, 2) +MERGE_INFLIGHT(merge_inflight_store2u, int32_t, int32_t, uint16_t, 2) +MERGE_INFLIGHT(merge_inflight_store4s, int32_t, int32_t, int32_t, 4) +MERGE_INFLIGHT(merge_inflight_store4u, int32_t, int32_t, uint32_t, 4) +MERGE_INFLIGHT(merge_inflight_store8u, int64_t, int64_t, int64_t, 8) + +#define CHECK_NOSHUF(DST, VA, SZ, SIGN) \ + do { \ + if (slot == 0 && env->pkt_has_store_s1) { \ + DST = HELPER(merge_inflight_store##SZ##SIGN)(env, VA, DST); \ + } \ + } while (0) + +static inline uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint8_t retval; + get_user_u8(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 1, u); + return retval; +} + +static inline uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint16_t retval; + get_user_u16(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 2, u); + return retval; +} + +static inline uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint32_t retval; + get_user_u32(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 4, u); + return retval; +} + +static inline uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint64_t retval; + get_user_u64(retval, vaddr); + CHECK_NOSHUF(retval, vaddr, 8, u); + return retval; +} + +/* Helpful for printing intermediate values within instructions */ +void HELPER(debug_value)(CPUHexagonState *env, int32_t value) +{ + HEX_DEBUG_LOG("value = 0x%x\n", value); +} + +void HELPER(debug_value_i64)(CPUHexagonState *env, int64_t value) +{ + HEX_DEBUG_LOG("value_i64 = 0x%lx\n", value); +} + +static void cancel_slot(CPUHexagonState *env, uint32_t slot) +{ + HEX_DEBUG_LOG("Slot %d cancelled\n", slot); + env->slot_cancelled |= (1 << slot); +} + +/* These macros can be referenced in the generated helper functions */ +#define warn(...) /* Nothing */ +#define fatal(...) g_assert_not_reached(); + +#define BOGUS_HELPER(tag) \ + printf("ERROR: bogus helper: " #tag "\n") + +#include "helper_funcs_generated.h" +