From patchwork Thu Oct 29 23:58:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 11867947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46DDE139F for ; Fri, 30 Oct 2020 00:08:29 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B99FE20756 for ; Fri, 30 Oct 2020 00:08:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="T/JO9GPr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B99FE20756 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYHxz-0003LP-Fh for patchwork-qemu-devel@patchwork.kernel.org; Thu, 29 Oct 2020 20:08:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYHos-00086J-KZ for qemu-devel@nongnu.org; Thu, 29 Oct 2020 19:59:02 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:54410) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kYHoo-0004L0-Ts for qemu-devel@nongnu.org; Thu, 29 Oct 2020 19:59:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604015938; x=1635551938; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Q8NssF2GtH77S/CnR7zeX2jFLUyMIgx7wph8YdrbK4=; b=T/JO9GPrtRBc6umYbWFouM8ltmVvxY9G/NbjYXkMl8JSh9GDc0CdT7rz 02zdFPBDYXQ/w1muL9+XslKzNe3bYrOEdRX9zDQUcB1wazNksFTXarHrR C9ucvpXzpKw7dL3V/VvS+74FApJp3SdMlb0Lwpn9YWEj2jIL7w5YFDjGD s=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2020 16:58:54 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 29 Oct 2020 16:58:53 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D9BC54115; Thu, 29 Oct 2020 18:58:53 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v5 15/33] Hexagon (target/hexagon/arch.[ch]) utility functions Date: Thu, 29 Oct 2020 18:58:32 -0500 Message-Id: <1604015931-23005-16-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> References: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:All patches CC here" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 35 ++++++ target/hexagon/arch.c | 294 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h new file mode 100644 index 0000000..cf14480 --- /dev/null +++ b/target/hexagon/arch.h @@ -0,0 +1,35 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ARCH_H +#define HEXAGON_ARCH_H + +#include "qemu/osdep.h" +#include "qemu/int128.h" + +extern uint64_t interleave(uint32_t odd, uint32_t even); +extern uint64_t deinterleave(uint64_t src); +extern uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c); +extern int32_t conv_round(int32_t a, int n); +extern void arch_fpop_start(CPUHexagonState *env); +extern void arch_fpop_end(CPUHexagonState *env); +extern int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, + int *adjust, float_status *fp_status); +extern int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status); + +#endif diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c new file mode 100644 index 0000000..16002bf --- /dev/null +++ b/target/hexagon/arch.c @@ -0,0 +1,294 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "fpu/softfloat.h" +#include "cpu.h" +#include "fma_emu.h" +#include "arch.h" +#include "macros.h" + +#define SF_BIAS 127 +#define SF_MAXEXP 254 +#define SF_MANTBITS 23 +#define float32_nan make_float32(0xffffffff) + +#define BITS_MASK_8 0x5555555555555555ULL +#define PAIR_MASK_8 0x3333333333333333ULL +#define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL +#define BYTE_MASK_8 0x00ff00ff00ff00ffULL +#define HALF_MASK_8 0x0000ffff0000ffffULL +#define WORD_MASK_8 0x00000000ffffffffULL + +uint64_t interleave(uint32_t odd, uint32_t even) +{ + /* Convert to long long */ + uint64_t myodd = odd; + uint64_t myeven = even; + /* First, spread bits out */ + myodd = (myodd | (myodd << 16)) & HALF_MASK_8; + myeven = (myeven | (myeven << 16)) & HALF_MASK_8; + myodd = (myodd | (myodd << 8)) & BYTE_MASK_8; + myeven = (myeven | (myeven << 8)) & BYTE_MASK_8; + myodd = (myodd | (myodd << 4)) & NYBL_MASK_8; + myeven = (myeven | (myeven << 4)) & NYBL_MASK_8; + myodd = (myodd | (myodd << 2)) & PAIR_MASK_8; + myeven = (myeven | (myeven << 2)) & PAIR_MASK_8; + myodd = (myodd | (myodd << 1)) & BITS_MASK_8; + myeven = (myeven | (myeven << 1)) & BITS_MASK_8; + /* Now OR together */ + return myeven | (myodd << 1); +} + +uint64_t deinterleave(uint64_t src) +{ + /* Get odd and even bits */ + uint64_t myodd = ((src >> 1) & BITS_MASK_8); + uint64_t myeven = (src & BITS_MASK_8); + + /* Unspread bits */ + myeven = (myeven | (myeven >> 1)) & PAIR_MASK_8; + myodd = (myodd | (myodd >> 1)) & PAIR_MASK_8; + myeven = (myeven | (myeven >> 2)) & NYBL_MASK_8; + myodd = (myodd | (myodd >> 2)) & NYBL_MASK_8; + myeven = (myeven | (myeven >> 4)) & BYTE_MASK_8; + myodd = (myodd | (myodd >> 4)) & BYTE_MASK_8; + myeven = (myeven | (myeven >> 8)) & HALF_MASK_8; + myodd = (myodd | (myodd >> 8)) & HALF_MASK_8; + myeven = (myeven | (myeven >> 16)) & WORD_MASK_8; + myodd = (myodd | (myodd >> 16)) & WORD_MASK_8; + + /* Return odd bits in upper half */ + return myeven | (myodd << 32); +} + +uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c) +{ + uint64_t tmpa, tmpb, tmpc; + tmpa = fGETUWORD(0, a); + tmpb = fGETUWORD(0, b); + tmpc = tmpa + tmpb + c; + tmpa = fGETUWORD(1, a); + tmpb = fGETUWORD(1, b); + tmpc = tmpa + tmpb + fGETUWORD(1, tmpc); + tmpc = fGETUWORD(1, tmpc); + return tmpc; +} + +int32_t conv_round(int32_t a, int n) +{ + int64_t val; + + if (n == 0) { + val = a; + } else if ((a & ((1 << (n - 1)) - 1)) == 0) { /* N-1..0 all zero? */ + /* Add LSB from int part */ + val = ((fSE32_64(a)) + (int64_t) (((uint32_t) ((1 << n) & a)) >> 1)); + } else { + val = ((fSE32_64(a)) + (1 << (n - 1))); + } + + val = val >> n; + return (int32_t)val; +} + +/* Floating Point Stuff */ + +static const int softfloat_roundingmodes[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, +}; + +void arch_fpop_start(CPUHexagonState *env) +{ + set_float_exception_flags(0, &env->fp_status); + set_float_rounding_mode( + softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)], + &env->fp_status); +} + +#define RAISE_FP_EXCEPTION \ + do {} while (0) /* Not modelled in qemu user mode */ + +#define SOFTFLOAT_TEST_FLAG(FLAG, MYF, MYE) \ + do { \ + if (flags & FLAG) { \ + if (GET_USR_FIELD(USR_##MYF) == 0) { \ + SET_USR_FIELD(USR_##MYF, 1); \ + if (GET_USR_FIELD(USR_##MYE)) { \ + RAISE_FP_EXCEPTION; \ + } \ + } \ + } \ + } while (0) + +void arch_fpop_end(CPUHexagonState *env) +{ + int flags = get_float_exception_flags(&env->fp_status); + if (flags != 0) { + SOFTFLOAT_TEST_FLAG(float_flag_inexact, FPINPF, FPINPE); + SOFTFLOAT_TEST_FLAG(float_flag_divbyzero, FPDBZF, FPDBZE); + SOFTFLOAT_TEST_FLAG(float_flag_invalid, FPINVF, FPINVE); + SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE); + SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE); + } +} + +static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_status) +{ + float32 b = make_float32((SF_BIAS + p) << SF_MANTBITS); + return float32_mul(a, b, fp_status); +} + +int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust, + float_status *fp_status) +{ + int n_exp; + int d_exp; + int ret = 0; + float32 RsV, RtV, RdV; + int PeV = 0; + RsV = *Rs; + RtV = *Rt; + if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) { + if (extract32(RsV & RtV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_any_nan(RsV)) { + if (extract32(RsV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_any_nan(RtV)) { + /* or put NaN in num/den fixup? */ + if (extract32(RtV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) { + /* or put Inf in num fixup? */ + RdV = RsV = RtV = float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RsV) && float32_is_zero(RtV)) { + /* or put zero in num fixup? */ + RdV = RsV = RtV = float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RtV)) { + /* or put Inf in num fixup? */ + uint8_t RsV_sign = float32_is_neg(RsV); + uint8_t RtV_sign = float32_is_neg(RtV); + RsV = infinite_float32(RsV_sign ^ RtV_sign); + RtV = float32_one; + RdV = float32_one; + if (float32_is_infinity(RsV)) { + float_raise(float_flag_divbyzero, fp_status); + } + } else if (float32_is_infinity(RtV)) { + RsV = make_float32(0x80000000 & (RsV ^ RtV)); + RtV = float32_one; + RdV = float32_one; + } else if (float32_is_zero(RsV)) { + /* Does this just work itself out? */ + /* No, 0/Inf causes problems. */ + RsV = make_float32(0x80000000 & (RsV ^ RtV)); + RtV = float32_one; + RdV = float32_one; + } else if (float32_is_infinity(RsV)) { + uint8_t RsV_sign = float32_is_neg(RsV); + uint8_t RtV_sign = float32_is_neg(RtV); + RsV = infinite_float32(RsV_sign ^ RtV_sign); + RtV = float32_one; + RdV = float32_one; + } else { + PeV = 0x00; + /* Basic checks passed */ + n_exp = float32_getexp(RsV); + d_exp = float32_getexp(RtV); + if ((n_exp - d_exp + SF_BIAS) <= SF_MANTBITS) { + /* Near quotient underflow / inexact Q */ + PeV = 0x80; + RtV = float32_mul_pow2(RtV, -64, fp_status); + RsV = float32_mul_pow2(RsV, 64, fp_status); + } else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) { + /* Near quotient overflow */ + PeV = 0x40; + RtV = float32_mul_pow2(RtV, 32, fp_status); + RsV = float32_mul_pow2(RsV, -32, fp_status); + } else if (n_exp <= SF_MANTBITS + 2) { + RtV = float32_mul_pow2(RtV, 64, fp_status); + RsV = float32_mul_pow2(RsV, 64, fp_status); + } else if (d_exp <= 1) { + RtV = float32_mul_pow2(RtV, 32, fp_status); + RsV = float32_mul_pow2(RsV, 32, fp_status); + } else if (d_exp > 252) { + RtV = float32_mul_pow2(RtV, -32, fp_status); + RsV = float32_mul_pow2(RsV, -32, fp_status); + } + RdV = 0; + ret = 1; + } + *Rs = RsV; + *Rt = RtV; + *Rd = RdV; + *adjust = PeV; + return ret; +} + +int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status) +{ + float32 RsV, RdV; + int PeV = 0; + int r_exp; + int ret = 0; + RsV = *Rs; + if (float32_is_infinity(RsV)) { + if (extract32(RsV, 22, 1) == 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = float32_nan; + } else if (float32_lt(RsV, float32_zero, fp_status)) { + /* Negative nonzero values are NaN */ + float_raise(float_flag_invalid, fp_status); + RsV = float32_nan; + RdV = float32_nan; + } else if (float32_is_infinity(RsV)) { + /* or put Inf in num fixup? */ + RsV = infinite_float32(1); + RdV = infinite_float32(1); + } else if (float32_is_zero(RsV)) { + /* or put zero in num fixup? */ + RdV = float32_one; + } else { + PeV = 0x00; + /* Basic checks passed */ + r_exp = float32_getexp(RsV); + if (r_exp <= 24) { + RsV = float32_mul_pow2(RsV, 64, fp_status); + PeV = 0xe0; + } + RdV = 0; + ret = 1; + } + *Rs = RsV; + *Rd = RdV; + *adjust = PeV; + return ret; +}