| Message ID | 160457727672.17573.9713521384015502561.stgit@pasha-ThinkPad-X280 (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/openrisc: fix icount handling for timer instructions | expand |
On 11/5/20 3:54 AM, Pavel Dovgalyuk wrote: > This patch adds icount handling to mfspr/mtspr instructions > that may deal with hardware timers. > > Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> > --- > target/openrisc/translate.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) Looks correct, but it would be better not to duplicate the code from trans_l_mtspr, and use an is_jmp code (called DISAS_UPDATE_EXIT in some other targets). r~
On 06.11.2020 00:39, Richard Henderson wrote: > On 11/5/20 3:54 AM, Pavel Dovgalyuk wrote: >> This patch adds icount handling to mfspr/mtspr instructions >> that may deal with hardware timers. >> >> Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> >> --- >> target/openrisc/translate.c | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) > > Looks correct, but it would be better not to duplicate the code from > trans_l_mtspr, and use an is_jmp code (called DISAS_UPDATE_EXIT in some other > targets). mtspr includes the following comment: * Save all of the cpu state first, allowing it to be overwritten. Does it mean, that helper can overwrite the PC? Then the PC can't be updated in is_jmp handler at the end of instruction translation. Pavel Dovgalyuk
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index c6dce879f1..a9c81f8bd5 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -884,6 +884,18 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) gen_illegal_exception(dc); } else { TCGv spr = tcg_temp_new(); + + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + } + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); tcg_temp_free(spr); @@ -898,6 +910,9 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) } else { TCGv spr; + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } /* For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch * (although the SPR only exists for use by an ICE). Save all
This patch adds icount handling to mfspr/mtspr instructions that may deal with hardware timers. Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> --- target/openrisc/translate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)