| Message ID | 161290460478.11352.8933244555799318236.stgit@bmoger-ubuntu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] i386: Add the support for AMD EPYC 3rd generation processors | expand |
On Tue, Feb 09, 2021 at 03:04:05PM -0600, Babu Moger wrote: > Adds the support for AMD 3rd generation processors. The model > display for the new processor will be EPYC-Milan. > > Adds the following new feature bits on top of the feature bits from > the first and second generation EPYC models. > > pcid : Process context identifiers support > ibrs : Indirect Branch Restricted Speculation > ssbd : Speculative Store Bypass Disable > erms : Enhanced REP MOVSB/STOSB support > fsrm : Fast Short REP MOVSB support > invpcid : Invalidate processor context ID > pku : Protection keys support > svme-addr-chk : SVM instructions address check for #GP handling > > Depends on the following kernel commits: > 14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") > 3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") > 4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") > 4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") > 9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") > 3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") > 830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") > 4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") > c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") > 9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") > 30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") > 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") > c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") > a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") > fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") > 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") > 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") > > Signed-off-by: Babu Moger <babu.moger@amd.com> Queued, thanks!
Hello Babu, Have below doubt about exposed CPU flags between EPYC-Rome & EPYC-Milan family. Please see below. > Adds the support for AMD 3rd generation processors. The model > display for the new processor will be EPYC-Milan. > > Adds the following new feature bits on top of the feature bits from > the first and second generation EPYC models. > > pcid : Process context identifiers support > ibrs : Indirect Branch Restricted Speculation > ssbd : Speculative Store Bypass Disable > erms : Enhanced REP MOVSB/STOSB support > fsrm : Fast Short REP MOVSB support > invpcid : Invalidate processor context ID > pku : Protection keys support > svme-addr-chk : SVM instructions address check for #GP handling > > Depends on the following kernel commits: > 14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") > 3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") > 4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") > 4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") > 9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") > 3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") > 830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") > 4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") > c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") > 9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") > 30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") > 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") > c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") > a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") > fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") > 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") > 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") > > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > v2: Added svme-addr-chk. Also added all the dependent kernel commits in the log. > > v1: https://lore.kernel.org/qemu-devel/161133338780.27536.17735339269843944966.stgit@bmoger-ubuntu/ > > target/i386/cpu.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > target/i386/cpu.h | 4 ++ > 2 files changed, 110 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 9c3d2d60b7..24db7ed892 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > "clzero", NULL, "xsaveerptr", NULL, > NULL, NULL, NULL, NULL, > NULL, "wbnoinvd", NULL, NULL, > - "ibpb", NULL, NULL, "amd-stibp", > + "ibpb", NULL, "ibrs", "amd-stibp", > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, > @@ -1798,6 +1798,56 @@ static CPUCaches epyc_rome_cache_info = { > }, > }; > > +static CPUCaches epyc_milan_cache_info = { > + .l1d_cache = &(CPUCacheInfo) { > + .type = DATA_CACHE, > + .level = 1, > + .size = 32 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .l1i_cache = &(CPUCacheInfo) { > + .type = INSTRUCTION_CACHE, > + .level = 1, > + .size = 32 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .l2_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 2, > + .size = 512 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 1024, > + .lines_per_tag = 1, > + }, > + .l3_cache = &(CPUCacheInfo) { > + .type = UNIFIED_CACHE, > + .level = 3, > + .size = 32 * MiB, > + .line_size = 64, > + .associativity = 16, > + .partitions = 1, > + .sets = 32768, > + .lines_per_tag = 1, > + .self_init = true, > + .inclusive = true, > + .complex_indexing = true, > + }, > +}; > + > /* The following VMX features are not supported by KVM and are left out in the > * CPU definitions: > * > @@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = { > .model_id = "AMD EPYC-Rome Processor", > .cache_info = &epyc_rome_cache_info, > }, > + { > + .name = "EPYC-Milan", > + .level = 0xd, > + .vendor = CPUID_VENDOR_AMD, > + .family = 25, > + .model = 1, > + .stepping = 1, > + .features[FEAT_1_EDX] = > + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | > + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | > + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | > + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | > + CPUID_VME | CPUID_FP87, > + .features[FEAT_1_ECX] = > + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | > + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | > + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | > + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | > + CPUID_EXT_PCID, > + .features[FEAT_8000_0001_EDX] = > + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | > + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | > + CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] = > + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | > + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | > + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | > + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, > + .features[FEAT_8000_0008_EBX] = > + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | > + CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | > + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | > + CPUID_8000_0008_EBX_AMD_SSBD, Don't have SSBD flag exposed in default EPYC-Rome CPU configuration? Is there any reason for this? Or do we need to explicitly add it? Thanks, Pankaj > + .features[FEAT_7_0_EBX] = > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | > + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | > + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | > + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | > + CPUID_7_0_EBX_INVPCID, > + .features[FEAT_7_0_ECX] = > + CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, > + .features[FEAT_7_0_EDX] = > + CPUID_7_0_EDX_FSRM, > + .features[FEAT_XSAVE] = > + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | > + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > + .features[FEAT_SVM] = > + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, > + .xlevel = 0x8000001E, > + .model_id = "AMD EPYC-Milan Processor", > + .cache_info = &epyc_milan_cache_info, > + }, > }; > > /* KVM-specific features that are automatically added/removed > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 8d599bb5b8..888c3a59e2 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -816,8 +816,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) > /* Indirect Branch Prediction Barrier */ > #define CPUID_8000_0008_EBX_IBPB (1U << 12) > +/* Indirect Branch Restricted Speculation */ > +#define CPUID_8000_0008_EBX_IBRS (1U << 14) > /* Single Thread Indirect Branch Predictors */ > #define CPUID_8000_0008_EBX_STIBP (1U << 15) > +/* Speculative Store Bypass Disable */ > +#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) > > #define CPUID_XSAVE_XSAVEOPT (1U << 0) > #define CPUID_XSAVE_XSAVEC (1U << 1) > >
Hi Pankaj, On 2/23/21 10:32 AM, Pankaj Gupta wrote: > Hello Babu, > > Have below doubt about exposed CPU flags between EPYC-Rome & EPYC-Milan family. > Please see below. > >> Adds the support for AMD 3rd generation processors. The model >> display for the new processor will be EPYC-Milan. >> >> Adds the following new feature bits on top of the feature bits from >> the first and second generation EPYC models. >> >> pcid : Process context identifiers support >> ibrs : Indirect Branch Restricted Speculation >> ssbd : Speculative Store Bypass Disable >> erms : Enhanced REP MOVSB/STOSB support >> fsrm : Fast Short REP MOVSB support >> invpcid : Invalidate processor context ID >> pku : Protection keys support >> svme-addr-chk : SVM instructions address check for #GP handling >> >> Depends on the following kernel commits: >> 14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") >> 3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") >> 4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") >> 4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") >> 9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") >> 3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") >> 830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") >> 4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") >> c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") >> 9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") >> 30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") >> 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") >> c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") >> a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") >> fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") >> 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") >> 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- >> v2: Added svme-addr-chk. Also added all the dependent kernel commits in the log. >> >> v1: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F161133338780.27536.17735339269843944966.stgit%40bmoger-ubuntu%2F&data=04%7C01%7Cbabu.moger%40amd.com%7C4cdb8e4513444faf227d08d8d818b23b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637496947884399665%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=DepdBnCEp%2By069GaEmWnhETZ8saVkV9E8cExtzIyVLk%3D&reserved=0 >> >> target/i386/cpu.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++ >> target/i386/cpu.h | 4 ++ >> 2 files changed, 110 insertions(+), 1 deletion(-) >> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index 9c3d2d60b7..24db7ed892 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { >> "clzero", NULL, "xsaveerptr", NULL, >> NULL, NULL, NULL, NULL, >> NULL, "wbnoinvd", NULL, NULL, >> - "ibpb", NULL, NULL, "amd-stibp", >> + "ibpb", NULL, "ibrs", "amd-stibp", >> NULL, NULL, NULL, NULL, >> NULL, NULL, NULL, NULL, >> "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, >> @@ -1798,6 +1798,56 @@ static CPUCaches epyc_rome_cache_info = { >> }, >> }; >> >> +static CPUCaches epyc_milan_cache_info = { >> + .l1d_cache = &(CPUCacheInfo) { >> + .type = DATA_CACHE, >> + .level = 1, >> + .size = 32 * KiB, >> + .line_size = 64, >> + .associativity = 8, >> + .partitions = 1, >> + .sets = 64, >> + .lines_per_tag = 1, >> + .self_init = 1, >> + .no_invd_sharing = true, >> + }, >> + .l1i_cache = &(CPUCacheInfo) { >> + .type = INSTRUCTION_CACHE, >> + .level = 1, >> + .size = 32 * KiB, >> + .line_size = 64, >> + .associativity = 8, >> + .partitions = 1, >> + .sets = 64, >> + .lines_per_tag = 1, >> + .self_init = 1, >> + .no_invd_sharing = true, >> + }, >> + .l2_cache = &(CPUCacheInfo) { >> + .type = UNIFIED_CACHE, >> + .level = 2, >> + .size = 512 * KiB, >> + .line_size = 64, >> + .associativity = 8, >> + .partitions = 1, >> + .sets = 1024, >> + .lines_per_tag = 1, >> + }, >> + .l3_cache = &(CPUCacheInfo) { >> + .type = UNIFIED_CACHE, >> + .level = 3, >> + .size = 32 * MiB, >> + .line_size = 64, >> + .associativity = 16, >> + .partitions = 1, >> + .sets = 32768, >> + .lines_per_tag = 1, >> + .self_init = true, >> + .inclusive = true, >> + .complex_indexing = true, >> + }, >> +}; >> + >> /* The following VMX features are not supported by KVM and are left out in the >> * CPU definitions: >> * >> @@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = { >> .model_id = "AMD EPYC-Rome Processor", >> .cache_info = &epyc_rome_cache_info, >> }, >> + { >> + .name = "EPYC-Milan", >> + .level = 0xd, >> + .vendor = CPUID_VENDOR_AMD, >> + .family = 25, >> + .model = 1, >> + .stepping = 1, >> + .features[FEAT_1_EDX] = >> + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | >> + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | >> + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | >> + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | >> + CPUID_VME | CPUID_FP87, >> + .features[FEAT_1_ECX] = >> + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | >> + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | >> + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | >> + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | >> + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | >> + CPUID_EXT_PCID, >> + .features[FEAT_8000_0001_EDX] = >> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | >> + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | >> + CPUID_EXT2_SYSCALL, >> + .features[FEAT_8000_0001_ECX] = >> + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | >> + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | >> + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | >> + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, >> + .features[FEAT_8000_0008_EBX] = >> + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | >> + CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | >> + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | >> + CPUID_8000_0008_EBX_AMD_SSBD, > > Don't have SSBD flag exposed in default EPYC-Rome CPU configuration? > Is there any reason for this? > Or do we need to explicitly add it? I think we missed it when we added EPYC-Rome model. I was going to add it sometime soon. As you know users can still add it with "+ssbd" if required. Thanks Babu > > Thanks, > Pankaj > >> + .features[FEAT_7_0_EBX] = >> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | >> + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | >> + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | >> + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | >> + CPUID_7_0_EBX_INVPCID, >> + .features[FEAT_7_0_ECX] = >> + CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, >> + .features[FEAT_7_0_EDX] = >> + CPUID_7_0_EDX_FSRM, >> + .features[FEAT_XSAVE] = >> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | >> + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, >> + .features[FEAT_6_EAX] = >> + CPUID_6_EAX_ARAT, >> + .features[FEAT_SVM] = >> + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, >> + .xlevel = 0x8000001E, >> + .model_id = "AMD EPYC-Milan Processor", >> + .cache_info = &epyc_milan_cache_info, >> + }, >> }; >> >> /* KVM-specific features that are automatically added/removed >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h >> index 8d599bb5b8..888c3a59e2 100644 >> --- a/target/i386/cpu.h >> +++ b/target/i386/cpu.h >> @@ -816,8 +816,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; >> #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) >> /* Indirect Branch Prediction Barrier */ >> #define CPUID_8000_0008_EBX_IBPB (1U << 12) >> +/* Indirect Branch Restricted Speculation */ >> +#define CPUID_8000_0008_EBX_IBRS (1U << 14) >> /* Single Thread Indirect Branch Predictors */ >> #define CPUID_8000_0008_EBX_STIBP (1U << 15) >> +/* Speculative Store Bypass Disable */ >> +#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) >> >> #define CPUID_XSAVE_XSAVEOPT (1U << 0) >> #define CPUID_XSAVE_XSAVEC (1U << 1) >> >>
Hi Babu, > >> + .features[FEAT_8000_0008_EBX] = > >> + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | > >> + CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | > >> + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | > >> + CPUID_8000_0008_EBX_AMD_SSBD, > > > > Don't have SSBD flag exposed in default EPYC-Rome CPU configuration? > > Is there any reason for this? > > Or do we need to explicitly add it? > > I think we missed it when we added EPYC-Rome model. I was going to add it > sometime soon. As you know users can still add it with "+ssbd" if required. Thanks for clarifying. I also see CPUID_8000_0008_EBX_IBRS missing for Rome. Will it be okay if we add them now for Rome? diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a53446e6a..b495116545 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4161,7 +4161,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0008_EBX] = CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | - CPUID_8000_0008_EBX_STIBP, + CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_IBRS | + CPUID_8000_0008_EBX_AMD_SSBD, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
Hi Pankaj, > -----Original Message----- > From: Pankaj Gupta <pankaj.gupta.linux@gmail.com> > Sent: Wednesday, February 24, 2021 2:19 AM > To: Moger, Babu <Babu.Moger@amd.com> > Cc: Paolo Bonzini <pbonzini@redhat.com>; richard.henderson@linaro.org; > Eduardo Habkost <ehabkost@redhat.com>; Qemu Developers <qemu- > devel@nongnu.org> > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation > processors > > Hi Babu, > > > >> + .features[FEAT_8000_0008_EBX] = > > >> + CPUID_8000_0008_EBX_CLZERO | > CPUID_8000_0008_EBX_XSAVEERPTR | > > >> + CPUID_8000_0008_EBX_WBNOINVD | > CPUID_8000_0008_EBX_IBPB | > > >> + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | > > >> + CPUID_8000_0008_EBX_AMD_SSBD, > > > > > > Don't have SSBD flag exposed in default EPYC-Rome CPU configuration? > > > Is there any reason for this? > > > Or do we need to explicitly add it? > > > > I think we missed it when we added EPYC-Rome model. I was going to add > > it sometime soon. As you know users can still add it with "+ssbd" if required. > > Thanks for clarifying. I also see CPUID_8000_0008_EBX_IBRS missing for Rome. > Will it be okay if we add them now for Rome? It is normally added as v2 for compatibility. Like this. diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 24db7ed892..f721d0db78 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = { .xlevel = 0x8000001E, .model_id = "AMD EPYC-Rome Processor", .cache_info = &epyc_rome_cache_info, + .versions = (X86CPUVersionDefinition[]) { + { .version = 1 }, + { + .version = 2, + .props = (PropValue[]) { + { "ibrs", "on" }, + { "amd-ssbd", "on" }, + { "model-id", + "AMD EPYC-Rome Processor" }, + { /* end of list */ } + } + }, + { /* end of list */ } + } }, { .name = "EPYC-Milan", > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > 6a53446e6a..b495116545 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4161,7 +4161,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > .features[FEAT_8000_0008_EBX] = > CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR > | > CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | > - CPUID_8000_0008_EBX_STIBP, > + CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_IBRS | > + CPUID_8000_0008_EBX_AMD_SSBD, > .features[FEAT_7_0_EBX] = > CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > CPUID_7_0_EBX_AVX2 | > CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | > CPUID_7_0_EBX_RDSEED |
Patchew URL: https://patchew.org/QEMU/cd9a84a3-f151-fa00-0b34-2652824bbbfc@amd.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: cd9a84a3-f151-fa00-0b34-2652824bbbfc@amd.com Subject: RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu - [tag update] patchew/20210219153348.41861-1-mreitz@redhat.com -> patchew/20210219153348.41861-1-mreitz@redhat.com - [tag update] patchew/20210222141514.2646278-1-f4bug@amsat.org -> patchew/20210222141514.2646278-1-f4bug@amsat.org - [tag update] patchew/20210223225250.23945-1-vgoyal@redhat.com -> patchew/20210223225250.23945-1-vgoyal@redhat.com - [tag update] patchew/20210224131142.1952027-1-berrange@redhat.com -> patchew/20210224131142.1952027-1-berrange@redhat.com - [tag update] patchew/20210224135255.253837-1-kwolf@redhat.com -> patchew/20210224135255.253837-1-kwolf@redhat.com * [new tag] patchew/cd9a84a3-f151-fa00-0b34-2652824bbbfc@amd.com -> patchew/cd9a84a3-f151-fa00-0b34-2652824bbbfc@amd.com Switched to a new branch 'test' 982be90 i386: Add the support for AMD EPYC 3rd generation processors === OUTPUT BEGIN === ERROR: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 20 lines checked Commit 982be908c3d2 (i386: Add the support for AMD EPYC 3rd generation processors) has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/cd9a84a3-f151-fa00-0b34-2652824bbbfc@amd.com/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
> It is normally added as v2 for compatibility. Like this. o.k. Thanks! I will test this tomorrow. > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 24db7ed892..f721d0db78 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = { > .xlevel = 0x8000001E, > .model_id = "AMD EPYC-Rome Processor", > .cache_info = &epyc_rome_cache_info, > + .versions = (X86CPUVersionDefinition[]) { > + { .version = 1 }, > + { > + .version = 2, > + .props = (PropValue[]) { > + { "ibrs", "on" }, > + { "amd-ssbd", "on" }, > + { "model-id", > + "AMD EPYC-Rome Processor" }, > + { /* end of list */ } > + } > + }, > + { /* end of list */ } > + } > }, > { > .name = "EPYC-Milan",
Hi Babu, I tried to test below patch for AMD EPYC Rome CPU and I got below error [1]: Also, I noticed SSBD CPU flag for guest was still available even without this patch, I noticed that for the guest, AMD_SSBD not got set. Guest: 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 edx=0x00000000 [1] [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 (native_write_msr+0x4/0x20) [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: 0xffffffff9245c772 (native_read_msr+0x2/0x40) Thanks, Pankaj > > It is normally added as v2 for compatibility. Like this. > > o.k. Thanks! > I will test this tomorrow. > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index 24db7ed892..f721d0db78 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = { > > .xlevel = 0x8000001E, > > .model_id = "AMD EPYC-Rome Processor", > > .cache_info = &epyc_rome_cache_info, > > + .versions = (X86CPUVersionDefinition[]) { > > + { .version = 1 }, > > + { > > + .version = 2, > > + .props = (PropValue[]) { > > + { "ibrs", "on" }, > > + { "amd-ssbd", "on" }, > > + { "model-id", > > + "AMD EPYC-Rome Processor" }, > > + { /* end of list */ } > > + } > > + }, > > + { /* end of list */ } > > + } > > }, > > { > > .name = "EPYC-Milan",
Pankaj, > -----Original Message----- > From: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > Sent: Monday, March 1, 2021 10:46 AM > To: Pankaj Gupta <pankaj.gupta.linux@gmail.com> > Cc: Moger, Babu <Babu.Moger@amd.com>; Paolo Bonzini > <pbonzini@redhat.com>; richard.henderson@linaro.org; Eduardo Habkost > <ehabkost@redhat.com>; Qemu Developers <qemu-devel@nongnu.org> > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation > processors > > Hi Babu, > > I tried to test below patch for AMD EPYC Rome CPU and I got below error [1]: > > Also, I noticed SSBD CPU flag for guest was still available even without this > patch, I noticed that for the guest, AMD_SSBD not got set. > > Guest: > 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 > edx=0x00000000 > > [1] > [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to > write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 > (native_write_msr+0x4/0x20) > [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 > [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 > [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 > > 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: > 0xffffffff9245c772 (native_read_msr+0x2/0x40) I did not see any problem with these patches. My guest setup. # lscpu |grep -o ssbd ssbd [root@rome-vm ~]# uname -r 4.18.0-147.el8.x86_64 [root@rome-vm ~]# cat /etc/redhat-release Red Hat Enterprise Linux release 8.1 (Ootpa) # wrmsr 0x48 7 [root@rome-vm ~]# rdmsr 0x48 7 My host os. # uname -r 4.18.0-193.el8.x86_64 [root@rome images]# cat /etc/redhat-release Red Hat Enterprise Linux release 8.2 Beta (Ootpa) Also, I only see ssbd feature when add this patch(EPYC-Rome-v2). Otherwise, I don’t see ssbd feature. Thanks Babu > > Thanks, > Pankaj > > > > It is normally added as v2 for compatibility. Like this. > > > > o.k. Thanks! > > I will test this tomorrow. > > > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > > > 24db7ed892..f721d0db78 100644 > > > --- a/target/i386/cpu.c > > > +++ b/target/i386/cpu.c > > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = { > > > .xlevel = 0x8000001E, > > > .model_id = "AMD EPYC-Rome Processor", > > > .cache_info = &epyc_rome_cache_info, > > > + .versions = (X86CPUVersionDefinition[]) { > > > + { .version = 1 }, > > > + { > > > + .version = 2, > > > + .props = (PropValue[]) { > > > + { "ibrs", "on" }, > > > + { "amd-ssbd", "on" }, > > > + { "model-id", > > > + "AMD EPYC-Rome Processor" }, > > > + { /* end of list */ } > > > + } > > > + }, > > > + { /* end of list */ } > > > + } > > > }, > > > { > > > .name = "EPYC-Milan",
> > Hi Babu, > > > > I tried to test below patch for AMD EPYC Rome CPU and I got below error [1]: > > > > Also, I noticed SSBD CPU flag for guest was still available even without this > > patch, I noticed that for the guest, AMD_SSBD not got set. > > > > Guest: > > 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 > > edx=0x00000000 > > > > [1] > > [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to > > write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 > > (native_write_msr+0x4/0x20) > > [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 > > [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 > > [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 > > > > 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: > > 0xffffffff9245c772 (native_read_msr+0x2/0x40) > > I did not see any problem with these patches. > My guest setup. > # lscpu |grep -o ssbd > ssbd > [root@rome-vm ~]# uname -r > 4.18.0-147.el8.x86_64 > [root@rome-vm ~]# cat /etc/redhat-release > Red Hat Enterprise Linux release 8.1 (Ootpa) > # wrmsr 0x48 7 > [root@rome-vm ~]# rdmsr 0x48 > 7 > > > My host os. > # uname -r > 4.18.0-193.el8.x86_64 > [root@rome images]# cat /etc/redhat-release > Red Hat Enterprise Linux release 8.2 Beta (Ootpa) > > Also, I only see ssbd feature when add this patch(EPYC-Rome-v2). > Otherwise, I don’t see ssbd feature. Thanks for checking! Can you also see the ibrs feature inside guest with this patch? Thanks, Pankaj > > Thanks > Babu > > > > > > Thanks, > > Pankaj > > > > > > It is normally added as v2 for compatibility. Like this. > > > > > > o.k. Thanks! > > > I will test this tomorrow. > > > > > > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > > > > 24db7ed892..f721d0db78 100644 > > > > --- a/target/i386/cpu.c > > > > +++ b/target/i386/cpu.c > > > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = { > > > > .xlevel = 0x8000001E, > > > > .model_id = "AMD EPYC-Rome Processor", > > > > .cache_info = &epyc_rome_cache_info, > > > > + .versions = (X86CPUVersionDefinition[]) { > > > > + { .version = 1 }, > > > > + { > > > > + .version = 2, > > > > + .props = (PropValue[]) { > > > > + { "ibrs", "on" }, > > > > + { "amd-ssbd", "on" }, > > > > + { "model-id", > > > > + "AMD EPYC-Rome Processor" }, > > > > + { /* end of list */ } > > > > + } > > > > + }, > > > > + { /* end of list */ } > > > > + } > > > > }, > > > > { > > > > .name = "EPYC-Milan",
> -----Original Message----- > From: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > Sent: Monday, March 1, 2021 2:22 PM > To: Moger, Babu <Babu.Moger@amd.com> > Cc: Pankaj Gupta <pankaj.gupta.linux@gmail.com>; Paolo Bonzini > <pbonzini@redhat.com>; richard.henderson@linaro.org; Eduardo Habkost > <ehabkost@redhat.com>; Qemu Developers <qemu-devel@nongnu.org> > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation > processors > > > > Hi Babu, > > > > > > I tried to test below patch for AMD EPYC Rome CPU and I got below error > [1]: > > > > > > Also, I noticed SSBD CPU flag for guest was still available even > > > without this patch, I noticed that for the guest, AMD_SSBD not got set. > > > > > > Guest: > > > 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 > > > edx=0x00000000 > > > > > > [1] > > > [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to > > > write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 > > > (native_write_msr+0x4/0x20) > > > [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 > > > [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 > > > [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 > > > > > > 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: > > > 0xffffffff9245c772 (native_read_msr+0x2/0x40) > > > > I did not see any problem with these patches. > > My guest setup. > > # lscpu |grep -o ssbd > > ssbd > > [root@rome-vm ~]# uname -r > > 4.18.0-147.el8.x86_64 > > [root@rome-vm ~]# cat /etc/redhat-release Red Hat Enterprise Linux > > release 8.1 (Ootpa) # wrmsr 0x48 7 [root@rome-vm ~]# rdmsr 0x48 > > 7 > > > > > > My host os. > > # uname -r > > 4.18.0-193.el8.x86_64 > > [root@rome images]# cat /etc/redhat-release Red Hat Enterprise Linux > > release 8.2 Beta (Ootpa) > > > > Also, I only see ssbd feature when add this patch(EPYC-Rome-v2). > > Otherwise, I don’t see ssbd feature. > > Thanks for checking! > Can you also see the ibrs feature inside guest with this patch? Yes, The feature is available with this patch. Otherwise it is not available. [root@rome-vm ~]# lscpu |grep -o ibrs ibrs > > Thanks, > Pankaj > > > > Thanks > > Babu > > > > > > > > > > Thanks, > > > Pankaj > > > > > > > > It is normally added as v2 for compatibility. Like this. > > > > > > > > o.k. Thanks! > > > > I will test this tomorrow. > > > > > > > > > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > > > > > 24db7ed892..f721d0db78 100644 > > > > > --- a/target/i386/cpu.c > > > > > +++ b/target/i386/cpu.c > > > > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = > { > > > > > .xlevel = 0x8000001E, > > > > > .model_id = "AMD EPYC-Rome Processor", > > > > > .cache_info = &epyc_rome_cache_info, > > > > > + .versions = (X86CPUVersionDefinition[]) { > > > > > + { .version = 1 }, > > > > > + { > > > > > + .version = 2, > > > > > + .props = (PropValue[]) { > > > > > + { "ibrs", "on" }, > > > > > + { "amd-ssbd", "on" }, > > > > > + { "model-id", > > > > > + "AMD EPYC-Rome Processor" }, > > > > > + { /* end of list */ } > > > > > + } > > > > > + }, > > > > > + { /* end of list */ } > > > > > + } > > > > > }, > > > > > { > > > > > .name = "EPYC-Milan",
Hi Babu, I confirm I can see both the ssbd & irbs features in guest with the below patch. There was some issue at my end, Sorry! for the confusion. Can you please post the official patch for inclusion. Best regards, Pankaj On Mon, Mar 1, 2021 at 9:38 PM Babu Moger <babu.moger@amd.com> wrote: > > > > > -----Original Message----- > > From: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> > > Sent: Monday, March 1, 2021 2:22 PM > > To: Moger, Babu <Babu.Moger@amd.com> > > Cc: Pankaj Gupta <pankaj.gupta.linux@gmail.com>; Paolo Bonzini > > <pbonzini@redhat.com>; richard.henderson@linaro.org; Eduardo Habkost > > <ehabkost@redhat.com>; Qemu Developers <qemu-devel@nongnu.org> > > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation > > processors > > > > > > Hi Babu, > > > > > > > > I tried to test below patch for AMD EPYC Rome CPU and I got below error > > [1]: > > > > > > > > Also, I noticed SSBD CPU flag for guest was still available even > > > > without this patch, I noticed that for the guest, AMD_SSBD not got set. > > > > > > > > Guest: > > > > 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 > > > > edx=0x00000000 > > > > > > > > [1] > > > > [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to > > > > write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 > > > > (native_write_msr+0x4/0x20) > > > > [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 > > > > [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 > > > > [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 > > > > > > > > 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: > > > > 0xffffffff9245c772 (native_read_msr+0x2/0x40) > > > > > > I did not see any problem with these patches. > > > My guest setup. > > > # lscpu |grep -o ssbd > > > ssbd > > > [root@rome-vm ~]# uname -r > > > 4.18.0-147.el8.x86_64 > > > [root@rome-vm ~]# cat /etc/redhat-release Red Hat Enterprise Linux > > > release 8.1 (Ootpa) # wrmsr 0x48 7 [root@rome-vm ~]# rdmsr 0x48 > > > 7 > > > > > > > > > My host os. > > > # uname -r > > > 4.18.0-193.el8.x86_64 > > > [root@rome images]# cat /etc/redhat-release Red Hat Enterprise Linux > > > release 8.2 Beta (Ootpa) > > > > > > Also, I only see ssbd feature when add this patch(EPYC-Rome-v2). > > > Otherwise, I don’t see ssbd feature. > > > > Thanks for checking! > > Can you also see the ibrs feature inside guest with this patch? > > Yes, The feature is available with this patch. Otherwise it is not available. > [root@rome-vm ~]# lscpu |grep -o ibrs > ibrs > > > > > Thanks, > > Pankaj > > > > > > Thanks > > > Babu > > > > > > > > > > > > > > Thanks, > > > > Pankaj > > > > > > > > > > It is normally added as v2 for compatibility. Like this. > > > > > > > > > > o.k. Thanks! > > > > > I will test this tomorrow. > > > > > > > > > > > > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > > > > > > 24db7ed892..f721d0db78 100644 > > > > > > --- a/target/i386/cpu.c > > > > > > +++ b/target/i386/cpu.c > > > > > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = > > { > > > > > > .xlevel = 0x8000001E, > > > > > > .model_id = "AMD EPYC-Rome Processor", > > > > > > .cache_info = &epyc_rome_cache_info, > > > > > > + .versions = (X86CPUVersionDefinition[]) { > > > > > > + { .version = 1 }, > > > > > > + { > > > > > > + .version = 2, > > > > > > + .props = (PropValue[]) { > > > > > > + { "ibrs", "on" }, > > > > > > + { "amd-ssbd", "on" }, > > > > > > + { "model-id", > > > > > > + "AMD EPYC-Rome Processor" }, > > > > > > + { /* end of list */ } > > > > > > + } > > > > > > + }, > > > > > > + { /* end of list */ } > > > > > > + } > > > > > > }, > > > > > > { > > > > > > .name = "EPYC-Milan",
Pankaj, Sure. I will add signoff from you if it is fine with you. Signed-off-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com> Let me know. Thanks Babu On 3/2/21 12:38 PM, Pankaj Gupta wrote: > Hi Babu, > > I confirm I can see both the ssbd & irbs features in guest with the > below patch. There was some issue at my end, Sorry! for the confusion. > Can you please post the official patch for inclusion. > > Best regards, > Pankaj > > On Mon, Mar 1, 2021 at 9:38 PM Babu Moger <babu.moger@amd.com> wrote: >> >> >> >>> -----Original Message----- >>> From: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> >>> Sent: Monday, March 1, 2021 2:22 PM >>> To: Moger, Babu <Babu.Moger@amd.com> >>> Cc: Pankaj Gupta <pankaj.gupta.linux@gmail.com>; Paolo Bonzini >>> <pbonzini@redhat.com>; richard.henderson@linaro.org; Eduardo Habkost >>> <ehabkost@redhat.com>; Qemu Developers <qemu-devel@nongnu.org> >>> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation >>> processors >>> >>>>> Hi Babu, >>>>> >>>>> I tried to test below patch for AMD EPYC Rome CPU and I got below error >>> [1]: >>>>> >>>>> Also, I noticed SSBD CPU flag for guest was still available even >>>>> without this patch, I noticed that for the guest, AMD_SSBD not got set. >>>>> >>>>> Guest: >>>>> 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 >>>>> edx=0x00000000 >>>>> >>>>> [1] >>>>> [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to >>>>> write 0x0000000000000000) at rIP: 0xffffffff9245c9e4 >>>>> (native_write_msr+0x4/0x20) >>>>> [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50 >>>>> [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80 >>>>> [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0 >>>>> >>>>> 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP: >>>>> 0xffffffff9245c772 (native_read_msr+0x2/0x40) >>>> >>>> I did not see any problem with these patches. >>>> My guest setup. >>>> # lscpu |grep -o ssbd >>>> ssbd >>>> [root@rome-vm ~]# uname -r >>>> 4.18.0-147.el8.x86_64 >>>> [root@rome-vm ~]# cat /etc/redhat-release Red Hat Enterprise Linux >>>> release 8.1 (Ootpa) # wrmsr 0x48 7 [root@rome-vm ~]# rdmsr 0x48 >>>> 7 >>>> >>>> >>>> My host os. >>>> # uname -r >>>> 4.18.0-193.el8.x86_64 >>>> [root@rome images]# cat /etc/redhat-release Red Hat Enterprise Linux >>>> release 8.2 Beta (Ootpa) >>>> >>>> Also, I only see ssbd feature when add this patch(EPYC-Rome-v2). >>>> Otherwise, I don’t see ssbd feature. >>> >>> Thanks for checking! >>> Can you also see the ibrs feature inside guest with this patch? >> >> Yes, The feature is available with this patch. Otherwise it is not available. >> [root@rome-vm ~]# lscpu |grep -o ibrs >> ibrs >> >>> >>> Thanks, >>> Pankaj >>>> >>>> Thanks >>>> Babu >>>> >>>> >>>>> >>>>> Thanks, >>>>> Pankaj >>>>> >>>>>>> It is normally added as v2 for compatibility. Like this. >>>>>> >>>>>> o.k. Thanks! >>>>>> I will test this tomorrow. >>>>>> >>>>>>> >>>>>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c index >>>>>>> 24db7ed892..f721d0db78 100644 >>>>>>> --- a/target/i386/cpu.c >>>>>>> +++ b/target/i386/cpu.c >>>>>>> @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = >>> { >>>>>>> .xlevel = 0x8000001E, >>>>>>> .model_id = "AMD EPYC-Rome Processor", >>>>>>> .cache_info = &epyc_rome_cache_info, >>>>>>> + .versions = (X86CPUVersionDefinition[]) { >>>>>>> + { .version = 1 }, >>>>>>> + { >>>>>>> + .version = 2, >>>>>>> + .props = (PropValue[]) { >>>>>>> + { "ibrs", "on" }, >>>>>>> + { "amd-ssbd", "on" }, >>>>>>> + { "model-id", >>>>>>> + "AMD EPYC-Rome Processor" }, >>>>>>> + { /* end of list */ } >>>>>>> + } >>>>>>> + }, >>>>>>> + { /* end of list */ } >>>>>>> + } >>>>>>> }, >>>>>>> { >>>>>>> .name = "EPYC-Milan",
> Pankaj, Sure. > > I will add signoff from you if it is fine with you. Sure. Thank you! > > Signed-off-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com> Please use: Pankaj Gupta <pankaj.gupta@cloud.ionos.com > Thanks, Pankaj
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9c3d2d60b7..24db7ed892 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "clzero", NULL, "xsaveerptr", NULL, NULL, NULL, NULL, NULL, NULL, "wbnoinvd", NULL, NULL, - "ibpb", NULL, NULL, "amd-stibp", + "ibpb", NULL, "ibrs", "amd-stibp", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, @@ -1798,6 +1798,56 @@ static CPUCaches epyc_rome_cache_info = { }, }; +static CPUCaches epyc_milan_cache_info = { + .l1d_cache = &(CPUCacheInfo) { + .type = DATA_CACHE, + .level = 1, + .size = 32 * KiB, + .line_size = 64, + .associativity = 8, + .partitions = 1, + .sets = 64, + .lines_per_tag = 1, + .self_init = 1, + .no_invd_sharing = true, + }, + .l1i_cache = &(CPUCacheInfo) { + .type = INSTRUCTION_CACHE, + .level = 1, + .size = 32 * KiB, + .line_size = 64, + .associativity = 8, + .partitions = 1, + .sets = 64, + .lines_per_tag = 1, + .self_init = 1, + .no_invd_sharing = true, + }, + .l2_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .level = 2, + .size = 512 * KiB, + .line_size = 64, + .associativity = 8, + .partitions = 1, + .sets = 1024, + .lines_per_tag = 1, + }, + .l3_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .level = 3, + .size = 32 * MiB, + .line_size = 64, + .associativity = 16, + .partitions = 1, + .sets = 32768, + .lines_per_tag = 1, + .self_init = true, + .inclusive = true, + .complex_indexing = true, + }, +}; + /* The following VMX features are not supported by KVM and are left out in the * CPU definitions: * @@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = { .model_id = "AMD EPYC-Rome Processor", .cache_info = &epyc_rome_cache_info, }, + { + .name = "EPYC-Milan", + .level = 0xd, + .vendor = CPUID_VENDOR_AMD, + .family = 25, + .model = 1, + .stepping = 1, + .features[FEAT_1_EDX] = + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_PCID, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, + .features[FEAT_8000_0008_EBX] = + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | + CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | + CPUID_8000_0008_EBX_AMD_SSBD, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | + CPUID_7_0_EBX_INVPCID, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_FSRM, + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .features[FEAT_SVM] = + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, + .xlevel = 0x8000001E, + .model_id = "AMD EPYC-Milan Processor", + .cache_info = &epyc_milan_cache_info, + }, }; /* KVM-specific features that are automatically added/removed diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8d599bb5b8..888c3a59e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -816,8 +816,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Indirect Branch Prediction Barrier */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) +/* Indirect Branch Restricted Speculation */ +#define CPUID_8000_0008_EBX_IBRS (1U << 14) /* Single Thread Indirect Branch Predictors */ #define CPUID_8000_0008_EBX_STIBP (1U << 15) +/* Speculative Store Bypass Disable */ +#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) #define CPUID_XSAVE_XSAVEOPT (1U << 0) #define CPUID_XSAVE_XSAVEC (1U << 1)
Adds the support for AMD 3rd generation processors. The model display for the new processor will be EPYC-Milan. Adds the following new feature bits on top of the feature bits from the first and second generation EPYC models. pcid : Process context identifiers support ibrs : Indirect Branch Restricted Speculation ssbd : Speculative Store Bypass Disable erms : Enhanced REP MOVSB/STOSB support fsrm : Fast Short REP MOVSB support invpcid : Invalidate processor context ID pku : Protection keys support svme-addr-chk : SVM instructions address check for #GP handling Depends on the following kernel commits: 14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") 3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") 4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") 4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") 9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") 3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") 830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") 4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") 9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") 30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") Signed-off-by: Babu Moger <babu.moger@amd.com> --- v2: Added svme-addr-chk. Also added all the dependent kernel commits in the log. v1: https://lore.kernel.org/qemu-devel/161133338780.27536.17735339269843944966.stgit@bmoger-ubuntu/ target/i386/cpu.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 4 ++ 2 files changed, 110 insertions(+), 1 deletion(-)