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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:50:54 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , Yoshinori Sato Subject: [RFC PATCH 35/78] target/sh4: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:47:39 +0300 Message-Id: <1616b3baa81059284d7b58f2c5480f0b4dde439e.1697183082.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- target/sh4/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/helper.c b/target/sh4/helper.c index e02e7af607..c1cc5e82f4 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -56,131 +56,131 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) void superh_cpu_do_interrupt(CPUState *cs) { SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector = cs->exception_index; /* prioritize exceptions over interrupts */ do_exp = cs->exception_index != -1; do_irq = do_irq && (cs->exception_index == -1); if (env->sr & (1u << SR_BL)) { if (do_exp && cs->exception_index != 0x1e0) { /* In theory a masked exception generates a reset exception, which in turn jumps to the reset vector. However this only works when using a bootloader. When using a kernel and an initrd, they need to be reloaded and the program counter should be loaded with the kernel entry point. qemu_system_reset_request takes care of that. */ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); return; } if (do_irq && !env->in_sleep) { return; /* masked */ } } env->in_sleep = 0; if (do_irq) { irq_vector = sh_intc_get_pending_vector(env->intc_handle, (env->sr >> 4) & 0xf); if (irq_vector == -1) { return; /* masked */ } } if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *expname; switch (cs->exception_index) { case 0x0e0: expname = "addr_error"; break; case 0x040: expname = "tlb_miss"; break; case 0x0a0: expname = "tlb_violation"; break; case 0x180: expname = "illegal_instruction"; break; case 0x1a0: expname = "slot_illegal_instruction"; break; case 0x800: expname = "fpu_disable"; break; case 0x820: expname = "slot_fpu"; break; case 0x100: expname = "data_write"; break; case 0x060: expname = "dtlb_miss_write"; break; case 0x0c0: expname = "dtlb_violation_write"; break; case 0x120: expname = "fpu_exception"; break; case 0x080: expname = "initial_page_write"; break; case 0x160: expname = "trapa"; break; default: expname = do_irq ? "interrupt" : "???"; break; } qemu_log("exception 0x%03x [%s] raised\n", irq_vector, expname); log_cpu_state(cs, 0); } env->ssr = cpu_read_sr(env); env->spc = env->pc; env->sgr = env->gregs[15]; env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); env->lock_addr = -1; if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { /* Branch instruction should be executed again before delay slot. */ env->spc -= 2; /* Clear flags for exception/interrupt routine. */ env->flags &= ~TB_FLAG_DELAY_SLOT_MASK; } if (do_exp) { env->expevt = cs->exception_index; switch (cs->exception_index) { case 0x000: case 0x020: case 0x140: env->sr &= ~(1u << SR_FD); env->sr |= 0xf << 4; /* IMASK */ env->pc = 0xa0000000; break; case 0x040: case 0x060: env->pc = env->vbr + 0x400; break; case 0x160: env->spc += 2; /* special case for TRAPA */ - /* fall through */ + fallthrough; default: env->pc = env->vbr + 0x100; break; } return; } if (do_irq) { env->intevt = irq_vector; env->pc = env->vbr + 0x600; return; } }