@@ -734,4 +734,15 @@
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+/* Nothing to do for these in qemu, need to suppress compiler warnings */
+#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ RtV = RtV; \
+ } while (0)
+#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ } while (0)
+
#endif
@@ -326,6 +326,13 @@ void test_lsbnew(void)
check(result, 5);
}
+void test_l2fetch(void)
+{
+ /* These don't do anything in qemu, just make sure they don't assert */
+ asm volatile ("l2fetch(r0, r1)\n\t"
+ "l2fetch(r0, r3:2)\n\t");
+}
+
int main()
{
int res;
@@ -459,6 +466,8 @@ int main()
test_lsbnew();
+ test_l2fetch();
+
puts(err ? "FAIL" : "PASS");
return err;
}
@@ -493,6 +493,9 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------")
DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
+DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----")
+DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------")
+
/*******************************/
/* */
/* */
Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> --- target/hexagon/gen_tcg.h | 11 +++++++++++ tests/tcg/hexagon/misc.c | 9 +++++++++ target/hexagon/imported/encode_pp.def | 3 +++ 3 files changed, 23 insertions(+)