| Message ID | 1623330957-18354-1-git-send-email-cbrowy@avery-design.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0 | expand |
On Thu, 10 Jun 2021 09:15:57 -0400 Chris Browy <cbrowy@avery-design.com> wrote: > From: hchkuo <hchkuo@avery-design.com.tw> > > Macros for the vender ID of PCI-SIG mentioned in "PCIe Data Object > Exchange ECN, March 12, 2020" and the size of PCIe Data Object > Exchange. > > Signed-off-by: hchkuo <hchkuo@avery-design.com.tw> > Signed-off-by: Chris Browy <cbrowy@avery-design.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > include/hw/pci/pci_ids.h | 3 +++ > include/hw/pci/pcie_regs.h | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h > index 95f92d98e9..2656009cfe 100644 > --- a/include/hw/pci/pci_ids.h > +++ b/include/hw/pci/pci_ids.h > @@ -157,6 +157,9 @@ > > /* Vendors and devices. Sort key: vendor first, device next. */ > > +/* Ref: PCIe Data Object Exchange ECN, March 12, 2020, Table 7-x2 */ > +#define PCI_VENDOR_ID_PCI_SIG 0x0001 > + > #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 > #define PCI_DEVICE_ID_LSI_53C810 0x0001 > #define PCI_DEVICE_ID_LSI_53C895A 0x0012 > diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h > index 1db86b0ec4..963dc2e170 100644 > --- a/include/hw/pci/pcie_regs.h > +++ b/include/hw/pci/pcie_regs.h > @@ -179,4 +179,8 @@ typedef enum PCIExpLinkWidth { > #define PCI_ACS_VER 0x1 > #define PCI_ACS_SIZEOF 8 > > +/* DOE Capability Register Fields */ > +#define PCI_DOE_VER 0x1 > +#define PCI_DOE_SIZEOF 24 > + > #endif /* QEMU_PCIE_REGS_H */
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 95f92d98e9..2656009cfe 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -157,6 +157,9 @@ /* Vendors and devices. Sort key: vendor first, device next. */ +/* Ref: PCIe Data Object Exchange ECN, March 12, 2020, Table 7-x2 */ +#define PCI_VENDOR_ID_PCI_SIG 0x0001 + #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 #define PCI_DEVICE_ID_LSI_53C810 0x0001 #define PCI_DEVICE_ID_LSI_53C895A 0x0012 diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 1db86b0ec4..963dc2e170 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -179,4 +179,8 @@ typedef enum PCIExpLinkWidth { #define PCI_ACS_VER 0x1 #define PCI_ACS_SIZEOF 8 +/* DOE Capability Register Fields */ +#define PCI_DOE_VER 0x1 +#define PCI_DOE_SIZEOF 24 + #endif /* QEMU_PCIE_REGS_H */