Message ID | 165156202959.27941.9731161369415852149-15@git.sr.ht (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add tail agnostic behavior for rvv instructions | expand |
On Tue, May 3, 2022 at 9:55 AM ~eopxd <eopxd@git.sr.ht> wrote: > > From: eopXD <eop.chen@sifive.com> > > According to v-spec, tail agnostic behavior can be either kept as > undisturbed or set elements' bits to all 1s. To distinguish the > difference of tail policies, QEMU should be able to simulate the tail > agnostic behavior as "set tail elements' bits to all 1s". > > There are multiple possibility for agnostic elements according to > v-spec. The main intent of this patch-set tries to add option that > can distinguish between tail policies. Setting agnostic elements to > all 1s allows QEMU to express this. > > This commit adds option 'rvv_ta_all_1s' is added to enable the > behavior, it is default as disabled. > > Signed-off-by: eop Chen <eop.chen@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ddda4906ff..cd4cf4b41e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -810,6 +810,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), > > DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > + DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > DEFINE_PROP_END_OF_LIST(), > }; > > -- > 2.34.2 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..cd4cf4b41e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -810,6 +810,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), DEFINE_PROP_END_OF_LIST(), };