[1/3] target/mips: introduce generic Cavium Octeon CPU model

Commit Message

Pavel Dovgalyuk June 7, 2022, 8:59 a.m. UTC

This patch adds generic Octeon vCPU for providing
Octeon-specific instructions.

Signed-off-by: Pavel Dovgalyuk <[e-mail]>
---
 target/mips/cpu-defs.c.inc |   30 ++++++++++++++++++++++++++++++
 target/mips/mips-defs.h    |    1 +
 2 files changed, 31 insertions(+)

Comments

Richard Henderson June 7, 2022, 4:37 p.m. UTC | #1

On 6/7/22 01:59, Pavel Dovgalyuk wrote:
> +    {
> +        /*
> +         * A generic CPU providing MIPS64 Cavium Octeon features.
> +         * PRid is taken from Octeon 68xx CPUs
> +         * FIXME: Eventually this should be replaced by a real CPU model.
> +         */

You should just add the real cpu model.  No one will ever address this FIXME otherwise.


r~

Patch

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 582f940070..a60e48433c 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -921,6 +921,36 @@  const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /*
+         * A generic CPU providing MIPS64 Cavium Octeon features.
+         * PRid is taken from Octeon 68xx CPUs
+         * FIXME: Eventually this should be replaced by a real CPU model.
+         */
+        .name = "Octeon",
+        .CP0_PRid = 0x000D9100,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+                       (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
+                       (3U << CP0C4_MMUSizeExt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .CP0_PageGrain = (1 << CP0PG_ELPA),
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x12F8FFFF,
+        .SEGBITS = 42,
+        .PABITS = 49,
+        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 
 #endif
 };
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0a12d982a7..a6cebe0265 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -42,6 +42,7 @@ 
 #define INSN_LOONGSON2E   0x0000040000000000ULL
 #define INSN_LOONGSON2F   0x0000080000000000ULL
 #define INSN_LOONGSON3A   0x0000100000000000ULL
+#define INSN_OCTEON       0x0000200000000000ULL
 /*
  *   bits 52-63: vendor-specific ASEs
  */