@@ -856,6 +856,7 @@ struct ArchCPU {
DynamicGDBXMLInfo dyn_sysreg_xml;
DynamicGDBXMLInfo dyn_svereg_xml;
+ DynamicGDBXMLInfo dyn_m_systemreg_xml;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
@@ -1100,11 +1101,13 @@ int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
/*
- * Helpers to dynamically generates XML descriptions of the sysregs
- * and SVE registers. Returns the number of registers in each set.
+ * Helpers to dynamically generate XML descriptions of the sysregs,
+ * SVE registers, and M-profile system registers.
+ * Returns the number of registers in each set.
*/
int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
+int arm_gen_dynamic_m_systemreg_xml(CPUState *cpu, int base_reg);
/* Returns the dynamically generated XML for the gdb stub.
* Returns a pointer to the XML contents for the specified XML file or NULL
@@ -1496,6 +1499,11 @@ FIELD(SVCR, ZA, 1, 1)
FIELD(SMCR, LEN, 0, 4)
FIELD(SMCR, FA64, 31, 1)
+/*
+ * Read the CONTROL register as the MRS instruction would.
+ */
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
+
/* Write a new value to v7m.exception, thus transitioning into or out
* of Handler mode; this may result in a change of active stack pointer.
*/
@@ -322,6 +322,121 @@ int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
return cpu->dyn_sysreg_xml.num;
}
+/*
+ * Helper required because g_array_append_val is a macro
+ * that cannot handle string literals.
+ */
+static inline void g_array_append_str_literal(GArray *array, const char *str)
+{
+ g_array_append_val(array, str);
+}
+
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+ /* NOTE: This implementation shares a lot of logic with v7m_mrs. */
+ switch (reg) {
+
+ /*
+ * NOTE: MSP and PSP technically don't exist if the secure extension
+ * is present (replaced by MSP_S, MSP_NS, PSP_S, PSP_NS). Similar for
+ * MSPLIM and PSPLIM.
+ * However, the MRS instruction is still allowed to read from MSP and PSP,
+ * and will return the value associated with the current security state.
+ * We replicate this behavior for the convenience of users, who will see
+ * GDB behave similarly to their assembly code, even if they are oblivious
+ * to the security extension.
+ */
+ case 0: /* MSP */
+ return gdb_get_reg32(buf,
+ v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]);
+ case 1: /* PSP */
+ return gdb_get_reg32(buf,
+ v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp);
+ case 6: /* MSPLIM */
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.msplim[env->v7m.secure]);
+ case 7: /* PSPLIM */
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.psplim[env->v7m.secure]);
+
+ /*
+ * NOTE: PRIMASK, BASEPRI, and FAULTMASK are defined a bit differently
+ * from the SP family, but have similar banking behavior.
+ */
+ case 2: /* PRIMASK */
+ return gdb_get_reg32(buf, env->v7m.primask[env->v7m.secure]);
+ case 3: /* BASEPRI */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.basepri[env->v7m.secure]);
+ case 4: /* FAULTMASK */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.faultmask[env->v7m.secure]);
+
+ /*
+ * NOTE: CONTROL has a mix of banked and non-banked bits. We continue
+ * to emulate the MRS instruction. Unfortunately, this gives GDB no way
+ * to read the SFPA bit when the CPU is in a non-secure state.
+ */
+ case 5: /* CONTROL */
+ return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
+ }
+
+ return 0;
+}
+
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+ /* TODO: Implement. */
+ return 0;
+}
+
+int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int base_reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ GString *s = g_string_new(NULL);
+ DynamicGDBXMLInfo *info = &cpu->dyn_m_systemreg_xml;
+ bool is_v8 = arm_feature(env, ARM_FEATURE_V8);
+ bool is_main = arm_feature(env, ARM_FEATURE_M_MAIN);
+
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
+
+ g_autoptr(GArray) regs = g_array_new(false, true, sizeof(const char *));
+ /* 0 */ g_array_append_str_literal(regs, "msp");
+ /* 1 */ g_array_append_str_literal(regs, "psp");
+ /* 2 */ g_array_append_str_literal(regs, "primask");
+ /* 3 */ g_array_append_str_literal(regs, is_main ? "basepri" : "");
+ /* 4 */ g_array_append_str_literal(regs, is_main ? "faultmask" : "");
+ /* 5 */ g_array_append_str_literal(regs, "control");
+ /* 6 */ g_array_append_str_literal(regs, is_v8 ? "msplim" : "");
+ /* 7 */ g_array_append_str_literal(regs, is_v8 ? "psplim" : "");
+
+ for (int idx = 0; idx < regs->len; idx++) {
+ const char *name = g_array_index(regs, const char *, idx);
+ if (*name != '\0') {
+ g_string_append_printf(s,
+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+ name, base_reg);
+ }
+ base_reg++;
+ }
+ info->num = regs->len;
+
+ g_string_append_printf(s, "</feature>");
+ info->desc = g_string_free(s, false);
+ return info->num;
+}
+
struct TypeSize {
const char *gdb_type;
int size;
@@ -450,6 +565,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return cpu->dyn_sysreg_xml.desc;
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
return cpu->dyn_svereg_xml.desc;
+ } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
+ return cpu->dyn_m_systemreg_xml.desc;
}
return NULL;
}
@@ -493,6 +610,14 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
*/
gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
2, "arm-vfp-sysregs.xml", 0);
+ } else {
+ /* M-profile coprocessors. */
+ gdb_register_coprocessor(cs,
+ arm_gdb_get_m_systemreg,
+ arm_gdb_set_m_systemreg,
+ arm_gen_dynamic_m_systemreg_xml(
+ cs, cs->gdb_num_regs),
+ "arm-m-system.xml", 0);
}
}
if (cpu_isar_feature(aa32_mve, cpu)) {
@@ -53,7 +53,7 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
return xpsr_read(env) & mask;
}
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
{
uint32_t value = env->v7m.control[secure];
@@ -90,7 +90,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
case 0 ... 7: /* xPSR sub-fields */
return v7m_mrs_xpsr(env, reg, 0);
case 20: /* CONTROL */
- return v7m_mrs_control(env, 0);
+ return arm_v7m_mrs_control(env, 0);
default:
/* Unprivileged reads others as zero. */
return 0;
@@ -2420,7 +2420,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
case 0 ... 7: /* xPSR sub-fields */
return v7m_mrs_xpsr(env, reg, el);
case 20: /* CONTROL */
- return v7m_mrs_control(env, env->v7m.secure);
+ return arm_v7m_mrs_control(env, env->v7m.secure);
case 0x94: /* CONTROL_NS */
/*
* We have to handle this here because unprivileged Secure code