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02 Apr 2021 05:30:34 -0700 IronPort-SDR: k0sGHOl0Q2jfZGfSnheg+QV/Xb9hCWoLMm7kpXWElKlcZ/41GWPGr0iJnRSCFzzpgOXiECwfRZ L7nHy3NdHPzHL9yibxWDdlCNpEBR6EoMmYFEQNLdiUK0TN0rbVoD8qN+m0VCjbaekGiCD9wIhL JTSr9Vzhb1rhkQvULQ9KdeN0Ese47CrbE3bHLznDlYnBnnsytapkG9Z2D6d0qFF8d/Jppg54Yp R/Afp7xkUt03qZZbacvyyLzKMNNrW1Uf7XiLjXsnavVK2wHNY3GcOlA1TipGNEHaCZMlbtRKtX HbA= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.167.78]) by uls-op-cesaip01.wdc.com with ESMTP; 02 Apr 2021 05:50:27 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU Date: Fri, 2 Apr 2021 08:48:31 -0400 Message-Id: <169e1a3c65731c9ee5be4d0c394d53d0d8b2655d.1617367533.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=7197bd837=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: weiying_hou@outlook.com, Ethan.Lee.QNL@gmail.com, alistair.francis@wdc.com, alistair23@gmail.com, palmer@dabbelt.com, bmeng.cn@gmail.com, camiyoru@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The physical Ibex CPU has ePMP support and it's enabled for the OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d665681f90..244066a6fc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -202,6 +202,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); + qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); } static void rv32_imafcu_nommu_cpu_init(Object *obj)