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[v2,05/27] target/riscv: Fix CSR perm checking for HS mode

Message ID 1cb5cdbe67d8d9c489f6c0bedfc6c007e1f7243a.1572045716.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Hypervisor Extension v0.4 | expand

Commit Message

Alistair Francis Oct. 25, 2019, 11:23 p.m. UTC 
Update the CSR permission checking to work correctly when we are in
HS-mode.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..08956aa557 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -799,12 +799,22 @@  int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     /* check privileges and return -1 if check fails */
 #if !defined(CONFIG_USER_ONLY)
-    int csr_priv = get_field(csrno, 0x300);
+    int effective_priv = env->priv;
     int read_only = get_field(csrno, 0xC00) == 3;
-    if ((!env->debugger) && (env->priv < csr_priv)) {
-        return -1;
+
+    if (riscv_has_ext(env, RVH) &&
+        env->priv == PRV_S &&
+        !riscv_cpu_virt_enabled(env)) {
+        /*
+         * We are in S mode without virtualisation, therefore we are in HS Mode.
+         * Add 1 to the effective privledge level to allow us to access the
+         * Hypervisor CSRs.
+         */
+        effective_priv++;
     }
-    if (write_mask && read_only) {
+
+    if ((write_mask && read_only) ||
+        (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
         return -1;
     }
 #endif