diff mbox

[RFC,3/3] tcg: Add frontend support for fence gen in ARMv7

Message ID 20160524171856.1000-4-bobby.prani@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Pranith Kumar May 24, 2016, 5:18 p.m. UTC
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
 target-arm/translate.c | 11 +++++++++--
 tcg/tcg-op.h           |  5 +++++
 tcg/tcg-opc.h          |  2 +-
 3 files changed, 15 insertions(+), 3 deletions(-)

Comments

Richard Henderson May 25, 2016, 5:36 p.m. UTC | #1
On 05/24/2016 10:18 AM, Pranith Kumar wrote:
> -                /* We don't emulate caches so these are a no-op.  */
> +                if (TCG_TARGET_HAS_fence) {
> +                    tcg_gen_fence();
> +                }

This should then be unconditional.


r~
diff mbox

Patch

diff --git a/target-arm/translate.c b/target-arm/translate.c
index c946c0e..3407176 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7980,9 +7980,13 @@  static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 gen_clrex(s);
                 return;
             case 4: /* dsb */
+                ARCH(7);
+                return;
             case 5: /* dmb */
                 ARCH(7);
-                /* We don't emulate caches so these are a no-op.  */
+                if (TCG_TARGET_HAS_fence) {
+                    tcg_gen_fence();
+                }
                 return;
             case 6: /* isb */
                 /* We need to break the TB after this insn to execute
@@ -10330,8 +10334,11 @@  static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                             gen_clrex(s);
                             break;
                         case 4: /* dsb */
+                            break;
                         case 5: /* dmb */
-                            /* These execute as NOPs.  */
+                            if (TCG_TARGET_HAS_fence) {
+                                tcg_gen_fence();
+                            }
                             break;
                         case 6: /* isb */
                             /* We need to break the TB after this insn
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index c446d3d..1c7e8fc 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -261,6 +261,11 @@  static inline void tcg_gen_br(TCGLabel *l)
     tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
 }
 
+static inline void tcg_gen_fence(void)
+{
+    tcg_gen_op1(&tcg_ctx, INDEX_op_fence, 0);
+}
+
 /* Helper calls. */
 
 /* 32 bit ops */
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b772d90..4696cf1 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -42,7 +42,7 @@  DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 # define IMPL64  TCG_OPF_64BIT
 #endif
 
-DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS)
+DEF(fence, 0, 0, 0, 0)
 
 DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
 DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)