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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id w125sm22676221ywd.55.2016.05.24.10.19.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 May 2016 10:19:02 -0700 (PDT) From: Pranith Kumar To: Peter Maydell , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sergey Fedorov , qemu-arm@nongnu.org (open list:ARM), qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 24 May 2016 13:18:56 -0400 Message-Id: <20160524171856.1000-4-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160524171856.1000-1-bobby.prani@gmail.com> References: <20160524171856.1000-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::243 Subject: [Qemu-devel] [RFC PATCH 3/3] tcg: Add frontend support for fence gen in ARMv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Pranith Kumar --- target-arm/translate.c | 11 +++++++++-- tcg/tcg-op.h | 5 +++++ tcg/tcg-opc.h | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index c946c0e..3407176 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7980,9 +7980,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_clrex(s); return; case 4: /* dsb */ + ARCH(7); + return; case 5: /* dmb */ ARCH(7); - /* We don't emulate caches so these are a no-op. */ + if (TCG_TARGET_HAS_fence) { + tcg_gen_fence(); + } return; case 6: /* isb */ /* We need to break the TB after this insn to execute @@ -10330,8 +10334,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_clrex(s); break; case 4: /* dsb */ + break; case 5: /* dmb */ - /* These execute as NOPs. */ + if (TCG_TARGET_HAS_fence) { + tcg_gen_fence(); + } break; case 6: /* isb */ /* We need to break the TB after this insn diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index c446d3d..1c7e8fc 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -261,6 +261,11 @@ static inline void tcg_gen_br(TCGLabel *l) tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); } +static inline void tcg_gen_fence(void) +{ + tcg_gen_op1(&tcg_ctx, INDEX_op_fence, 0); +} + /* Helper calls. */ /* 32 bit ops */ diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index b772d90..4696cf1 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,7 +42,7 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif -DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS) +DEF(fence, 0, 0, 0, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)