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[80.15.154.113]) by smtp.googlemail.com with ESMTPSA id lf9sm15133703wjc.44.2016.05.26.09.36.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 May 2016 09:36:07 -0700 (PDT) From: Alvise Rigo To: mttcg@listserver.greensocs.com, alex.bennee@linaro.org Date: Thu, 26 May 2016 18:35:40 +0200 Message-Id: <20160526163549.3276-2-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160526163549.3276-1-a.rigo@virtualopensystems.com> References: <20160526163549.3276-1-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [RFC 01/10] exec: Introduce tcg_exclusive_{lock, unlock}() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, rth@twiddle.net, claudio.fontana@huawei.com, qemu-devel@nongnu.org, Alvise Rigo , cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add tcg_exclusive_{lock,unlock}() functions that will be used for making the emulation of LL and SC instructions thread safe. Signed-off-by: Alvise Rigo --- cpus.c | 2 ++ exec.c | 18 ++++++++++++++++++ include/qom/cpu.h | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/cpus.c b/cpus.c index 860e7ba..b9ec903 100644 --- a/cpus.c +++ b/cpus.c @@ -961,6 +961,8 @@ void qemu_init_cpu_loop(void) qemu_cond_init(&qemu_work_cond); qemu_mutex_init(&qemu_global_mutex); + qemu_spin_init(&cpu_exclusive_lock); + qemu_thread_get_self(&io_thread); safe_work = g_array_sized_new(TRUE, TRUE, sizeof(qemu_safe_work_item), 128); diff --git a/exec.c b/exec.c index a24b31c..1c72113 100644 --- a/exec.c +++ b/exec.c @@ -197,6 +197,24 @@ void cpu_exclusive_history_free(void) g_free(excl_history.c_array); } } + +__thread bool cpu_have_exclusive_lock; +QemuSpin cpu_exclusive_lock; +inline void tcg_exclusive_lock(void) +{ + if (!cpu_have_exclusive_lock) { + qemu_spin_lock(&cpu_exclusive_lock); + cpu_have_exclusive_lock = true; + } +} + +inline void tcg_exclusive_unlock(void) +{ + if (cpu_have_exclusive_lock) { + cpu_have_exclusive_lock = false; + qemu_spin_unlock(&cpu_exclusive_lock); + } +} #endif #if !defined(CONFIG_USER_ONLY) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 0f51870..019f06d 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -201,6 +201,11 @@ typedef struct CPUClass { void (*disas_set_info)(CPUState *cpu, disassemble_info *info); } CPUClass; +/* Protect cpu_exclusive_* variable .*/ +void tcg_exclusive_lock(void); +void tcg_exclusive_unlock(void); +extern QemuSpin cpu_exclusive_lock; + #ifdef HOST_WORDS_BIGENDIAN typedef struct icount_decr_u16 { uint16_t high;