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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id c62sm17150085ywf.12.2016.05.31.11.40.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 May 2016 11:40:36 -0700 (PDT) From: Pranith Kumar To: Blue Swirl , Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 31 May 2016 14:39:24 -0400 Message-Id: <20160531183928.29406-10-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160531183928.29406-1-bobby.prani@gmail.com> References: <20160531183928.29406-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-devel] [RFC v2 PATCH 09/13] tcg/sparc: Add support for fence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Blue Swirl Signed-off-by: Richard Henderson Signed-off-by: Pranith Kumar --- tcg/sparc/tcg-target.inc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index a611885..81f263f 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = { #define STWA (INSN_OP(3) | INSN_OP3(0x14)) #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) +#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -1450,6 +1452,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); break; + case INDEX_op_mb: + /* membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad */ + tcg_out32(s, MEMBAR | 15); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1551,6 +1558,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_st_i32, { "sZ", "A" } }, { INDEX_op_qemu_st_i64, { "SZ", "A" } }, + { INDEX_op_mb, { "r" } }, { -1 }, };