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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id c62sm17150085ywf.12.2016.05.31.11.40.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 May 2016 11:40:40 -0700 (PDT) From: Pranith Kumar To: Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 31 May 2016 14:39:28 -0400 Message-Id: <20160531183928.29406-14-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160531183928.29406-1-bobby.prani@gmail.com> References: <20160531183928.29406-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-devel] [RFC v2 PATCH 13/13] tcg: Generate fences only for SMP MTTCG guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP We need to generate fence instructions only for SMP MTTCG guests. This patch enforces that. Signed-off-by: Pranith Kumar --- tcg/tcg-op.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a6f01a7..eeb0d0c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -36,6 +36,8 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); #define TCGV_HIGH TCGV_HIGH_link_error #endif +extern int smp_cpus; + /* Note that this is optimized for sequential allocation during translate. Up to and including filling in the forward link immediately. We'll do proper termination of the end of the list after we finish translation. */ @@ -145,8 +147,9 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, void tcg_gen_mb(TCGArg a) { - /* ??? Enable only when MTTCG is enabled. */ - tcg_gen_op1(&tcg_ctx, INDEX_op_mb, 0); + if (qemu_tcg_mttcg_enabled() && smp_cpus > 1) { + tcg_gen_op1(&tcg_ctx, INDEX_op_mb, 0); + } } /* 32 bit ops */