From patchwork Tue May 31 18:39:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pranith Kumar X-Patchwork-Id: 9145497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4DE9B60777 for ; Tue, 31 May 2016 18:45:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 42D6F20072 for ; Tue, 31 May 2016 18:45:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 37C2520700; Tue, 31 May 2016 18:45:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C707A20072 for ; Tue, 31 May 2016 18:45:15 +0000 (UTC) Received: from localhost ([::1]:37853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7ofD-0007am-0F for patchwork-qemu-devel@patchwork.kernel.org; Tue, 31 May 2016 14:45:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7oaj-0003OZ-It for qemu-devel@nongnu.org; Tue, 31 May 2016 14:40:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7oac-0001Xv-2r for qemu-devel@nongnu.org; Tue, 31 May 2016 14:40:36 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34118) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7oab-0001XS-TT for qemu-devel@nongnu.org; Tue, 31 May 2016 14:40:30 -0400 Received: by mail-yw0-x242.google.com with SMTP id j74so20094973ywg.1 for ; Tue, 31 May 2016 11:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6iBbE/lZpW695529sShwUXIpYW5tYr31h2PxK/ABD7w=; b=Ns6LfMd2UJsNd774Xu2x9rzMAWJTppVz55PPeAkPVwwHoSkS8u8EcNOc33to9Wi81G wiRHobExa58Nizz77zeK829p0ql7q/819rpc5W0y1UHD7aVzp1R/6jzegssOtAA9yU/w 7aN3787IK9XFzBKitW/rsOmVjq8ZMGCmN/hJbKfDJDwkOW7VskWLKbHEK1xuVpd9IvCa o+whHDKBmbOjMEO20G+OyRkX0J9fZyypjLl0I5X4xFMoXl/5B7GNsmKgAQMA/NoZ4eWb SY7CSnKcZM1jyT8MhTwxLN4aW6+dmvOX3Lnp/t3etK9Zfmfjo5D8dmWXAtCkBB3yGLdj M05Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6iBbE/lZpW695529sShwUXIpYW5tYr31h2PxK/ABD7w=; b=kDgbAM5t9gCDxyPwgCPJZQn7b6bhY0oQ4d4uApAw2Pz2WjxDeBm8SyDKoI8lVxa8CJ eYSh23BQZGM45mlSDGP055bvQ6+S81ILg1gB1Frto7IW/JfP1GLCU0TC1m5AIF6Ia8Ud uIdZfqk4cohBfLMoeexz3rwkoPZROklAXuaSVXdfbhh9lFTiu6ohgryIGv/SH2vU0MbO 2gEqNo8ZVk+8czXIKvIIVcOCbOcQaqJPcSVa7o6MkE1Pms/IALkkWMdoEBBU1woNuZKr v77+L49fObHaoN0ntOQqvYxv8hm0bNmJb2mCh8U7REoSLNlkC2mKV6pPqdYks6UJXZE8 Vjnw== X-Gm-Message-State: ALyK8tJwo6ccRgbwap8b06fQlsO7RrjCUCvnYATS+H1ZCZPLw7rvTayU3NR8nW7DAalxgQ== X-Received: by 10.13.240.194 with SMTP id z185mr20595494ywe.317.1464720029533; Tue, 31 May 2016 11:40:29 -0700 (PDT) Received: from evgadesktop.attlocal.net (108-232-152-155.lightspeed.tukrga.sbcglobal.net. [108.232.152.155]) by smtp.gmail.com with ESMTPSA id c62sm17150085ywf.12.2016.05.31.11.40.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 May 2016 11:40:28 -0700 (PDT) From: Pranith Kumar To: Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 31 May 2016 14:39:16 -0400 Message-Id: <20160531183928.29406-2-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160531183928.29406-1-bobby.prani@gmail.com> References: <20160531183928.29406-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This commit introduces the TCGOpcode for memory barrier instruction. This opcode takes an argument which is the type of memory barrier which should be generated. Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/README | 17 +++++++++++++++++ tcg/tcg-op.c | 6 ++++++ tcg/tcg-op.h | 2 ++ tcg/tcg-opc.h | 2 ++ tcg/tcg.h | 8 ++++++++ 5 files changed, 35 insertions(+) diff --git a/tcg/README b/tcg/README index f4a8ac1..cfe79d7 100644 --- a/tcg/README +++ b/tcg/README @@ -402,6 +402,23 @@ double-word product T0. The later is returned in two single-word outputs. Similar to mulu2, except the two inputs T1 and T2 are signed. +********* Memory Barrier support + +* mb <$arg> + +Generate a target memory barrier instruction to ensure memory ordering as being +enforced by a corresponding guest memory barrier instruction. The ordering +enforced by the backend may be stricter than the ordering required by the guest. +It cannot be weaker. This opcode takes an optional constant argument if required +to generate the appropriate barrier instruction. The backend should take care to +emit the target barrier instruction only when necessary i.e., for SMP guests and +when MTTCG is enabled. + +The guest translators should generate this opcode for all guest instructions +which have ordering side effects. + +Please see docs/atomics.txt for more information on memory barriers. + ********* 64-bit guest on 32-bit host support The following opcodes are internal to TCG. Thus they are to be implemented by diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f554b86..a6f01a7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -143,6 +143,12 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, tcg_emit_op(ctx, opc, pi); } +void tcg_gen_mb(TCGArg a) +{ + /* ??? Enable only when MTTCG is enabled. */ + tcg_gen_op1(&tcg_ctx, INDEX_op_mb, 0); +} + /* 32 bit ops */ void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index c446d3d..40920fb 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -261,6 +261,8 @@ static inline void tcg_gen_br(TCGLabel *l) tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); } +void tcg_gen_mb(TCGArg a); + /* Helper calls. */ /* 32 bit ops */ diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 6d0410c..c0f3e83 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif +DEF(mb, 0, 1, 0, 0) + DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) diff --git a/tcg/tcg.h b/tcg/tcg.h index a46d17c..a1d59f7 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -385,6 +385,14 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1) #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) +/* TCGOpmb args */ +#define TCG_MB_FULL ((TCGArg)(0)) +#define TCG_MB_READ ((TCGArg)(1)) +#define TCG_MB_WRITE ((TCGArg)(2)) +#define TCG_MB_ACQUIRE ((TCGArg)(3)) +#define TCG_MB_RELEASE ((TCGArg)(4)) + + /* Conditions. Note that these are laid out for easy manipulation by the functions below: bit 0 is used for inverting;