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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id c62sm17150085ywf.12.2016.05.31.11.40.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 May 2016 11:40:31 -0700 (PDT) From: Pranith Kumar To: Andrzej Zaborowski , Richard Henderson , qemu-arm@nongnu.org (open list:ARM target), qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 31 May 2016 14:39:19 -0400 Message-Id: <20160531183928.29406-5-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160531183928.29406-1-bobby.prani@gmail.com> References: <20160531183928.29406-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-devel] [RFC v2 PATCH 04/13] tcg/arm: Add support for fence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index a914762..e88d8ce 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -305,6 +305,10 @@ typedef enum { INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + } ARMInsn; #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) @@ -1905,6 +1909,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; + case INDEX_op_mb: + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -1979,6 +1990,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_mb, { "r" } }, { -1 }, };