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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id c62sm17150085ywf.12.2016.05.31.11.40.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 May 2016 11:40:34 -0700 (PDT) From: Pranith Kumar To: Aurelien Jarno , Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Tue, 31 May 2016 14:39:21 -0400 Message-Id: <20160531183928.29406-7-bobby.prani@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160531183928.29406-1-bobby.prani@gmail.com> References: <20160531183928.29406-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::243 Subject: [Qemu-devel] [RFC v2 PATCH 06/13] tcg/mips: Add support for fence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson Signed-off-by: Pranith Kumar --- tcg/mips/tcg-target.inc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index b2a839a..fc9c7fb 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -292,6 +292,7 @@ typedef enum { OPC_JALR = OPC_SPECIAL | 0x09, OPC_MOVZ = OPC_SPECIAL | 0x0A, OPC_MOVN = OPC_SPECIAL | 0x0B, + OPC_SYNC = OPC_SPECIAL | 0x0F, OPC_MFHI = OPC_SPECIAL | 0x10, OPC_MFLO = OPC_SPECIAL | 0x12, OPC_MULT = OPC_SPECIAL | 0x18, @@ -1636,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const_args[4], const_args[5], true); break; + case INDEX_op_mb: + tcg_out32(s, OPC_SYNC); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } }, { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } }, #endif + + { INDEX_op_mb, { "r" } }, { -1 }, };