From patchwork Sat Jun 18 01:20:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: alarson@ddci.com X-Patchwork-Id: 9185299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8569B608A2 for ; Sat, 18 Jun 2016 01:21:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64D7127D45 for ; Sat, 18 Jun 2016 01:21:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56D402833F; Sat, 18 Jun 2016 01:21:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CB10227D45 for ; Sat, 18 Jun 2016 01:21:22 +0000 (UTC) Received: from localhost ([::1]:60887 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE4wq-0002do-Sq for patchwork-qemu-devel@patchwork.kernel.org; Fri, 17 Jun 2016 21:21:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51229) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE4wW-0002dB-5R for qemu-devel@nongnu.org; Fri, 17 Jun 2016 21:21:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bE4wS-0007dI-19 for qemu-devel@nongnu.org; Fri, 17 Jun 2016 21:20:59 -0400 Received: from wsip-184-183-10-181.ph.ph.cox.net ([184.183.10.181]:14591 helo=linux02.ddci.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE4wR-0007dC-P6; Fri, 17 Jun 2016 21:20:55 -0400 Received: from linux02.ddci.com (localhost.localdomain [127.0.0.1]) by linux02.ddci.com (8.13.8/8.13.8) with ESMTP id u5I1Kn5S021713; Fri, 17 Jun 2016 18:20:49 -0700 Received: (from alarson@localhost) by linux02.ddci.com (8.13.8/8.13.8/Submit) id u5I1Kl1o021712; Fri, 17 Jun 2016 18:20:47 -0700 Date: Fri, 17 Jun 2016 18:20:47 -0700 From: alarson@ddci.com Message-Id: <201606180120.u5I1Kl1o021712@linux02.ddci.com> X-Authentication-Warning: linux02.ddci.com: alarson set sender to alarson@ddci.com using -f To: agraf@suse.de, alarson@ddci.com, david@gibson.dropbear.id.au, qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 184.183.10.181 Subject: [Qemu-devel] [PATCH] target-ppc: Correct ppc3500_spin initial TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When e500 PPC is booted multi-core, the non-boot cores are started via the spin table. ppce500_spin.c:spin_kick() calls mmubooke_create_initial_mapping() to allocate a 64MB TLB entry, but the created TLB entry is only 256KB. The root cause is that the function computing the size of the TLB entry, namely booke206_page_size_to_tlb assumes MAS1.TSIZE as defined by latter PPC cores, specifically (n**4)KB. The result is then used by mmubooke_create_initial_mapping using MAS1_TSIZE_SHIFT, but MAS1_TSIZE_SHIFT is defined assuming TLB entries are (n**2)KB. I.e., a difference of shift=7 or shift=8. Simply changing MAS1_TSIZE_SHIFT from 7 to 8 is not appropriate since the macro is used elsewhere. Signed-off-by: Aaron Larson --- hw/ppc/ppce500_spin.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 76bd78b..7e38f0c 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -75,7 +75,11 @@ static void spin_reset(void *opaque) /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */ static inline hwaddr booke206_page_size_to_tlb(uint64_t size) { - return ctz32(size >> 10) >> 1; + /* The EREF indicates that TLB pages are (4 to the power of 2)KB, which + * corresponds to MAS1_TSIZE_SHIFT=8, but to support legacy processors that + * assume TLB pages are (2 to the power of 2)KB MAS1_TSIZE_SHIFT is + * currently 7. */ + return ctz32(size >> 10) >> (MAS1_TSIZE_SHIFT - 7); } static void mmubooke_create_initial_mapping(CPUPPCState *env,