From patchwork Sat Jun 18 04:03:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pranith Kumar X-Patchwork-Id: 9185395 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CB9F0601C0 for ; Sat, 18 Jun 2016 04:06:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B23A12835B for ; Sat, 18 Jun 2016 04:06:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A44F927E33; Sat, 18 Jun 2016 04:06:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 39F5927E33 for ; Sat, 18 Jun 2016 04:06:05 +0000 (UTC) Received: from localhost ([::1]:32964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7WG-0003fo-Br for patchwork-qemu-devel@patchwork.kernel.org; Sat, 18 Jun 2016 00:06:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7Vg-0003dA-Tf for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:05:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bE7Va-0005Ju-Rx for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:05:28 -0400 Received: from mail-yw0-x241.google.com ([2607:f8b0:4002:c05::241]:35297) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7Va-0005Jp-Mx for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:05:22 -0400 Received: by mail-yw0-x241.google.com with SMTP id z186so277139ywd.2 for ; Fri, 17 Jun 2016 21:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7pkv8qFsPsZdXzP8tGfPD3xvwXZ5WKu4qK4bLXeE0qI=; b=LjIiCT369c3hfaHYa7Dez4qNZb86RKkmb7wEsEcGjG7cVR+SQoNuFDQUAwnCNGk6ae 50uRbfzszrlTl0bE5wfFuwtqjwpO0Cs1jUUcg36erwBdvScxkPVasOMwh/DdfvaP03NJ Yz9T+V5C6iJYzjY+uzIPXDrFnBaaX6Jq0SWD+XL5A+f1rWPOGc2d3jjEeHR1EX6ROoV1 YL+LfkjralLsoZb76FFiNMeiBn323/2TxUs3fdYScMwNchn+O3zq6rsi4nT/5BxsPcQj KeS9WDY4ZiQPcrPpfaOeNMksmcbIfiZXZ9OU0148JEanpF8qIOO/GeAHZqgdBX0gSO1B o5FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7pkv8qFsPsZdXzP8tGfPD3xvwXZ5WKu4qK4bLXeE0qI=; b=m/Qvit/8I4oGcZTTyTCzkc4TYEouDSqOjJlJlNdW6yyFg7gVnQLgKgWYRyhcPot3co 5x+Big/jlR7ZBXhBJTs9epklATtXEHVy5UeAlO/2phyKPL0ljYSV+D/sjKbpr0xNzG9M IutBrDEfBHI7ekL2s42n1pNVboHJ6V69iq+FD6p1FUothVEhL/7QApTFaA00keQzBYFz MIXy40cm5z4Q8yzwvG9Z6KVw5DeEhxMmKwobcaNZpXrNuQJgu+eZT4cJUaXOVPMB1AKA Hi93Dg9BgBOmH1ajvXifmfAHSJv4VW1kosxalKwjyx3txOzbXF8uzd0RBliH7xTWuCZn EqIA== X-Gm-Message-State: ALyK8tLzgFt7UmMXPc5DRF6DkPfqIbhuSGVbQsNlcy1g61HmJIoBOjZYmZ+gnlhVSqCc7Q== X-Received: by 10.129.112.19 with SMTP id l19mr2898786ywc.222.1466222722313; Fri, 17 Jun 2016 21:05:22 -0700 (PDT) Received: from evgadesktop.attlocal.net (108-232-152-155.lightspeed.tukrga.sbcglobal.net. [108.232.152.155]) by smtp.gmail.com with ESMTPSA id q7sm19517992ywg.16.2016.06.17.21.05.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Jun 2016 21:05:21 -0700 (PDT) From: Pranith Kumar To: Richard Henderson , qemu-devel@nongnu.org (open list:i386 target) Date: Sat, 18 Jun 2016 00:03:31 -0400 Message-Id: <20160618040343.19517-3-bobby.prani@gmail.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160618040343.19517-1-bobby.prani@gmail.com> References: <20160618040343.19517-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::241 Subject: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: serge.fdrv@gmail.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Generate mfence/sfence/lfence instruction on SSE2 enabled processors. For older processors, generate a 'lock orl $0,0(%esp)' instruction which has full ordering semantics. Signed-off-by: Pranith Kumar [rth: Check for sse2, fallback to locked memory op otherwise.] Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 317484c..0748652 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -121,6 +121,16 @@ static bool have_cmov; # define have_cmov 0 #endif +/* For 32-bit, we are going to attempt to determine at runtime whether + sse2 support is available. */ +#if TCG_TARGET_REG_BITS == 64 || defined(__SSE2__) +# define have_sse2 1 +#elif defined(CONFIG_CPUID_H) && defined(bit_SSE2) +static bool have_sse2; +#else +# define have_sse2 0 +#endif + /* If bit_MOVBE is defined in cpuid.h (added in GCC version 4.6), we are going to attempt to determine at runtime whether movbe is available. */ #if defined(CONFIG_CPUID_H) && defined(bit_MOVBE) @@ -686,6 +696,32 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) } } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + if (have_sse2) { + tcg_out16(s, 0xae0f); + switch (a0 & TCG_MO_ALL) { + case TCG_MO_LD_LD: + /* lfence */ + tcg_out8(s, 0xe8); + break; + case TCG_MO_ST_ST: + /* sfence */ + tcg_out8(s, 0xf8); + break; + default: + /* mfence */ + tcg_out8(s, 0xf0); + break; + } + } else { + /* lock orl $0,0(%esp) */ + tcg_out8(s, 0xf0); + tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); + tcg_out8(s, 0); + } +} + static inline void tcg_out_push(TCGContext *s, int reg) { tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); @@ -2120,6 +2156,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_mb: + assert(args[0] != 0); + tcg_out_mb(s, args[0]); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2185,6 +2225,8 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, + { INDEX_op_mb, { } }, + #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, @@ -2362,6 +2404,11 @@ static void tcg_target_init(TCGContext *s) available, we'll use a small forward branch. */ have_cmov = (d & bit_CMOV) != 0; #endif +#ifndef have_sse2 + /* Likewise, almost all hardware supports SSE2, but we do + have a locked memory operation to use as a substitute. */ + have_sse2 = (d & bit_SSE2) != 0; +#endif #ifndef have_movbe /* MOVBE is only available on Intel Atom and Haswell CPUs, so we need to probe for it. */