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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id v68sm1634604ywg.31.2016.07.14.13.20.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jul 2016 13:20:57 -0700 (PDT) From: Pranith Kumar To: Stefan Weil , Richard Henderson , qemu-devel@nongnu.org (open list:All patches CC here) Date: Thu, 14 Jul 2016 16:20:22 -0400 Message-Id: <20160714202026.9727-11-bobby.prani@gmail.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-devel] [PATCH v4 10/14] tcg/tci: Add support for fence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, serge.fdrv@gmail.com, alex.bennee@linaro.org, qemu-devel@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Stefan Weil Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.inc.c | 3 +++ tci.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 3c47ea7..9dbf4d5 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -255,6 +255,7 @@ static const TCGTargetOpDef tcg_target_op_defs[] = { { INDEX_op_bswap32_i32, { R, R } }, #endif + { INDEX_op_mb, { } }, { -1 }, }; @@ -800,6 +801,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ diff --git a/tci.c b/tci.c index b488c0d..4bdc645 100644 --- a/tci.c +++ b/tci.c @@ -1236,6 +1236,10 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tcg_abort(); } break; + case INDEX_op_mb: + /* Ensure ordering for all kinds */ + smp_mb(); + break; default: TODO(); break;