diff mbox

[v4,08/14] tcg/s390: Add support for fence

Message ID 20160714202026.9727-9-bobby.prani@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Pranith Kumar July 14, 2016, 8:20 p.m. UTC 
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/s390/tcg-target.inc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Stefan Hajnoczi Oct. 16, 2016, 8:47 a.m. UTC | #1 
On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote:
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/s390/tcg-target.inc.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
> index 5a7495b..01aae35 100644
> --- a/tcg/s390/tcg-target.inc.c
> +++ b/tcg/s390/tcg-target.inc.c
> @@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
>  #define FACILITY_EXT_IMM	(1ULL << (63 - 21))
>  #define FACILITY_GEN_INST_EXT	(1ULL << (63 - 34))
>  #define FACILITY_LOAD_ON_COND   (1ULL << (63 - 45))
> +#define FACILITY_FAST_BCR_SER   FACILITY_LOAD_ON_COND
>  
>  static uint64_t facilities;
>  
> @@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tgen_deposit(s, args[0], args[2], args[3], args[4]);
>          break;
>  
> +    case INDEX_op_mb:
> +        /* The host memory model is quite strong, we simply need to
> +           serialize the instruction stream.  */
> +        if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
> +            tcg_out_insn(s, RR, BCR,
> +                         facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
> +        }

args[0] == TCG_MO_ALL is always false since frontends bitwise-OR
TCG_BAR_SC.

Did you mean:

switch (args[0] & TCG_MO_ALL) {
case TCG_MO_ALL: /* fall-through */
case TCG_MO_ST_LD:
    tcg_out_insn(s, RR, BCR,
                 facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
    break;
}

?
Pranith Kumar Oct. 16, 2016, 4:17 p.m. UTC | #2 
On Sun, Oct 16, 2016 at 4:47 AM, Stefan Hajnoczi <stefanha@gmail.com> wrote:
> On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote:
>> Cc: Alexander Graf <agraf@suse.de>
>> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>>  tcg/s390/tcg-target.inc.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
>> index 5a7495b..01aae35 100644
>> --- a/tcg/s390/tcg-target.inc.c
>> +++ b/tcg/s390/tcg-target.inc.c
>> @@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
>>  #define FACILITY_EXT_IMM     (1ULL << (63 - 21))
>>  #define FACILITY_GEN_INST_EXT        (1ULL << (63 - 34))
>>  #define FACILITY_LOAD_ON_COND   (1ULL << (63 - 45))
>> +#define FACILITY_FAST_BCR_SER   FACILITY_LOAD_ON_COND
>>
>>  static uint64_t facilities;
>>
>> @@ -2172,6 +2173,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>>          tgen_deposit(s, args[0], args[2], args[3], args[4]);
>>          break;
>>
>> +    case INDEX_op_mb:
>> +        /* The host memory model is quite strong, we simply need to
>> +           serialize the instruction stream.  */
>> +        if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
>> +            tcg_out_insn(s, RR, BCR,
>> +                         facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
>> +        }
>
> args[0] == TCG_MO_ALL is always false since frontends bitwise-OR
> TCG_BAR_SC.
>
> Did you mean:
>
> switch (args[0] & TCG_MO_ALL) {
> case TCG_MO_ALL: /* fall-through */
> case TCG_MO_ST_LD:
>     tcg_out_insn(s, RR, BCR,
>                  facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
>     break;
> }

Yup, that is what is intended. It looks like this patch was fixed by
rth when he merged it to do the correct thing. phew :)
diff mbox

Patch

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5a7495b..01aae35 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -343,6 +343,7 @@  static tcg_insn_unit *tb_ret_addr;
 #define FACILITY_EXT_IMM	(1ULL << (63 - 21))
 #define FACILITY_GEN_INST_EXT	(1ULL << (63 - 34))
 #define FACILITY_LOAD_ON_COND   (1ULL << (63 - 45))
+#define FACILITY_FAST_BCR_SER   FACILITY_LOAD_ON_COND
 
 static uint64_t facilities;
 
@@ -2172,6 +2173,15 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tgen_deposit(s, args[0], args[2], args[3], args[4]);
         break;
 
+    case INDEX_op_mb:
+        /* The host memory model is quite strong, we simply need to
+           serialize the instruction stream.  */
+        if (args[0] == TCG_MO_ALL || args[0] == TCG_MO_ST_LD) {
+            tcg_out_insn(s, RR, BCR,
+                         facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
+        }
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -2293,6 +2303,7 @@  static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
     { INDEX_op_deposit_i64, { "r", "0", "r" } },
 
+    { INDEX_op_mb, { } },
     { -1 },
 };