From patchwork Mon Jul 18 22:44:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 9235549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5A1F6602F0 for ; Mon, 18 Jul 2016 23:06:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B2341FF65 for ; Mon, 18 Jul 2016 23:06:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3FCEF252D2; Mon, 18 Jul 2016 23:06:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C6EE81FF65 for ; Mon, 18 Jul 2016 23:06:50 +0000 (UTC) Received: from localhost ([::1]:50774 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHcf-0000QR-T5 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 18 Jul 2016 19:06:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGn-0006e7-Tl for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bPHGl-0005XT-Q4 for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34513) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGl-0005XF-HP for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:11 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1E9AAC0799B9; Mon, 18 Jul 2016 22:44:11 +0000 (UTC) Received: from redhat.com (vpn1-7-82.ams2.redhat.com [10.36.7.82]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u6IMi6OL020835; Mon, 18 Jul 2016 18:44:07 -0400 Date: Tue, 19 Jul 2016 01:44:05 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20160719014405-mutt-send-email-mst@redhat.com> References: <1468881010-27229-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1468881010-27229-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Mon, 18 Jul 2016 22:44:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 16/55] acpi: add DMAR scope definition for root IOAPIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Peter Xu , Igor Mammedov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Xu To enable interrupt remapping for intel IOMMU device, each IOAPIC device in the system reported via ACPI MADT must be explicitly enumerated under one specific remapping hardware unit. This patch adds the root-complex IOAPIC into the default DMAR device. Please refer to VT-d spec 8.3.1.1 for more information. Signed-off-by: Peter Xu Signed-off-by: Peter Xu --- include/hw/acpi/acpi-defs.h | 13 +++++++++++++ include/hw/pci-host/q35.h | 8 ++++++++ hw/i386/acpi-build.c | 20 +++++++++++++++++--- 3 files changed, 38 insertions(+), 3 deletions(-) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index ea9be0b..41c1d95 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -571,6 +571,18 @@ enum { /* * Sub-structures for DMAR */ + +/* Device scope structure for DRHD. */ +struct AcpiDmarDeviceScope { + uint8_t entry_type; + uint8_t length; + uint16_t reserved; + uint8_t enumeration_id; + uint8_t bus; + uint16_t path[0]; /* list of dev:func pairs */ +} QEMU_PACKED; +typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope; + /* Type 0: Hardware Unit Definition */ struct AcpiDmarHardwareUnit { uint16_t type; @@ -579,6 +591,7 @@ struct AcpiDmarHardwareUnit { uint8_t reserved; uint16_t pci_segment; /* The PCI Segment associated with this unit */ uint64_t address; /* Base address of remapping hardware register-set */ + AcpiDmarDeviceScope scope[0]; } QEMU_PACKED; typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 0d64032..94486fd 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -179,4 +179,12 @@ typedef struct Q35PCIHost { uint64_t mch_mcfg_base(void); +/* + * Arbitary but unique BNF number for IOAPIC device. + * + * TODO: make sure there would have no conflict with real PCI bus + */ +#define Q35_PSEUDO_BUS_PLATFORM (0xff) +#define Q35_PSEUDO_DEVFN_IOAPIC (0x00) + #endif /* HW_Q35_H */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 06682f1..77c40d9 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -81,6 +81,9 @@ #define ACPI_BUILD_DPRINTF(fmt, ...) #endif +/* Default IOAPIC ID */ +#define ACPI_BUILD_IOAPIC_ID 0x0 + typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; @@ -384,7 +387,6 @@ build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) io_apic = acpi_data_push(table_data, sizeof *io_apic); io_apic->type = ACPI_APIC_IO; io_apic->length = sizeof(*io_apic); -#define ACPI_BUILD_IOAPIC_ID 0x0 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); io_apic->interrupt = cpu_to_le32(0); @@ -2468,6 +2470,9 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) AcpiDmarHardwareUnit *drhd; uint8_t dmar_flags = 0; X86IOMMUState *iommu = x86_iommu_get_default(); + AcpiDmarDeviceScope *scope = NULL; + /* Root complex IOAPIC use one path[0] only */ + size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); assert(iommu); if (iommu->intr_supported) { @@ -2479,13 +2484,22 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) dmar->flags = dmar_flags; /* DMAR Remapping Hardware Unit Definition structure */ - drhd = acpi_data_push(table_data, sizeof(*drhd)); + drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); - drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ + drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; drhd->pci_segment = cpu_to_le16(0); drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); + /* Scope definition for the root-complex IOAPIC. See VT-d spec + * 8.3.1 (version Oct. 2014 or later). */ + scope = &drhd->scope[0]; + scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ + scope->length = ioapic_scope_size; + scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; + scope->bus = Q35_PSEUDO_BUS_PLATFORM; + scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC); + build_header(linker, table_data, (void *)(table_data->data + dmar_start), "DMAR", table_data->len - dmar_start, 1, NULL, NULL); }