From patchwork Tue Jul 19 17:51:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 9238125 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B69DE602F0 for ; Tue, 19 Jul 2016 18:43:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6D1326A4D for ; Tue, 19 Jul 2016 18:43:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9BEC226E81; Tue, 19 Jul 2016 18:43:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 497CF26A4D for ; Tue, 19 Jul 2016 18:43:31 +0000 (UTC) Received: from localhost ([::1]:57933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPZzO-0003kn-7C for patchwork-qemu-devel@patchwork.kernel.org; Tue, 19 Jul 2016 14:43:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60958) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPZBL-0003WW-V7 for qemu-devel@nongnu.org; Tue, 19 Jul 2016 13:51:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bPZBK-00011s-0q for qemu-devel@nongnu.org; Tue, 19 Jul 2016 13:51:46 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50985) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPZBJ-00011i-RE for qemu-devel@nongnu.org; Tue, 19 Jul 2016 13:51:45 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 580F444813; Tue, 19 Jul 2016 17:51:45 +0000 (UTC) Received: from redhat.com (vpn1-7-82.ams2.redhat.com [10.36.7.82]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u6JHpevI008767; Tue, 19 Jul 2016 13:51:41 -0400 Date: Tue, 19 Jul 2016 20:51:40 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20160719175140.GA32695@redhat.com> References: <1468950176-31959-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1468950176-31959-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 19 Jul 2016 17:51:45 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL v2 14/55] intel_iommu: allow queued invalidation for IR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Eduardo Habkost , Peter Xu , Paolo Bonzini Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Xu Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e5f514c..b648e69 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -286,6 +286,8 @@ typedef struct VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_TYPE 0xf #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */ #define VTD_INV_DESC_IOTLB 0x2 +#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache + Invalidate Descriptor */ #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3ee5782..26e322a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1404,6 +1404,15 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; + case VTD_INV_DESC_IEC: + VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation " + "not implemented yet"); + /* + * Since currently we do not cache interrupt entries, we can + * just mark this descriptor as "good" and move on. + */ + break; + default: VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type " "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,