From patchwork Fri Aug 19 19:09:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 9290777 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7E26D6077B for ; Fri, 19 Aug 2016 19:11:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 736672953B for ; Fri, 19 Aug 2016 19:11:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6825A29542; Fri, 19 Aug 2016 19:11:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E892B2953B for ; Fri, 19 Aug 2016 19:11:11 +0000 (UTC) Received: from localhost ([::1]:58649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bapCB-0007LR-1t for patchwork-qemu-devel@patchwork.kernel.org; Fri, 19 Aug 2016 15:11:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bapBc-0007Is-EY for qemu-devel@nongnu.org; Fri, 19 Aug 2016 15:10:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bapBX-00021z-Qx for qemu-devel@nongnu.org; Fri, 19 Aug 2016 15:10:35 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:14605) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bapBX-00021m-L1 for qemu-devel@nongnu.org; Fri, 19 Aug 2016 15:10:31 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id AF124A957207E; Fri, 19 Aug 2016 20:10:16 +0100 (IST) Received: from localhost (10.100.200.35) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 19 Aug 2016 20:10:20 +0100 From: Paul Burton To: , Aurelien Jarno , Leon Alrae Date: Fri, 19 Aug 2016 20:09:00 +0100 Message-ID: <20160819190903.10974-5-paul.burton@imgtec.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160819190903.10974-1-paul.burton@imgtec.com> References: <20160819190903.10974-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.35] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 4/7] target-mips: Provide function to test if a CPU supports an ISA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Provide a new cpu_supports_isa function which allows callers to determine whether a CPU supports one of the ISA_ flags, by testing whether the associated struct mips_def_t sets the ISA flags in its insn_flags field. An example use of this is to allow boards which generate bootloader code to determine the properties of the CPU that will be used, for example whether the CPU is 64 bit or which architecture revision it implements. Signed-off-by: Paul Burton Reviewed-by: Leon Alrae --- target-mips/cpu.h | 1 + target-mips/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 5182dc7..cbd17df 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -812,6 +812,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ diff --git a/target-mips/translate.c b/target-mips/translate.c index bab52cb..c212e4f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20192,6 +20192,16 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +bool cpu_supports_isa(const char *cpu_model, unsigned int isa) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->insn_flags & isa) != 0; +} + void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));