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Violators will be prosecuted; Mon, 5 Sep 2016 09:52:50 +0100 X-IBM-Helo: d06dlp01.portsmouth.uk.ibm.com X-IBM-MailFrom: dahi@linux.vnet.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id DE9BE17D8042 for ; Mon, 5 Sep 2016 09:54:41 +0100 (BST) Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u858qoov10748260 for ; Mon, 5 Sep 2016 08:52:50 GMT Received: from d06av07.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u858qn65031492 for ; Mon, 5 Sep 2016 04:52:50 -0400 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u858qlQ4031408; Mon, 5 Sep 2016 04:52:49 -0400 From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Sep 2016 10:52:20 +0200 X-Mailer: git-send-email 2.8.4 In-Reply-To: <20160905085244.99980-1-dahi@linux.vnet.ibm.com> References: <20160905085244.99980-1-dahi@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16090508-0028-0000-0000-0000020DDC55 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16090508-0029-0000-0000-0000202D4C2F Message-Id: <20160905085244.99980-7-dahi@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-05_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1609050135 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [Patch v4 06/30] s390x/cpumodel: generate CPU feature group lists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, borntraeger@de.ibm.com, fiuczy@linux.vnet.ibm.com, cornelia.huck@de.ibm.com, imammedo@redhat.com, jdenemar@redhat.com, mimu@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Feature groups will be very helpful to reduce the amount of features typically available in sane configurations. E.g. the MSA facilities introduced loads of subfunctions, which could - in theory - go away in the future, but we want to avoid reporting hundrets of features to the user if usually all of them are in place. Groups only contain features that were introduced in one shot, not just random features. Therefore, groups can never change. This is an important property regarding migration. Acked-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target-s390x/gen-features.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/target-s390x/gen-features.c b/target-s390x/gen-features.c index 8f02c29..dfc7659 100644 --- a/target-s390x/gen-features.c +++ b/target-s390x/gen-features.c @@ -182,6 +182,35 @@ S390_FEAT_MSA_EXT_5, \ S390_FEAT_PPNO_SHA_512_DRNG +/* cpu feature groups */ +static uint16_t group_PLO[] = { + S390_FEAT_GROUP_PLO, +}; +static uint16_t group_TOD_CLOCK_STEERING[] = { + S390_FEAT_GROUP_TOD_CLOCK_STEERING, +}; +static uint16_t group_GEN13_PTFF[] = { + S390_FEAT_GROUP_GEN13_PTFF, +}; +static uint16_t group_MSA[] = { + S390_FEAT_GROUP_MSA, +}; +static uint16_t group_MSA_EXT_1[] = { + S390_FEAT_GROUP_MSA_EXT_1, +}; +static uint16_t group_MSA_EXT_2[] = { + S390_FEAT_GROUP_MSA_EXT_2, +}; +static uint16_t group_MSA_EXT_3[] = { + S390_FEAT_GROUP_MSA_EXT_3, +}; +static uint16_t group_MSA_EXT_4[] = { + S390_FEAT_GROUP_MSA_EXT_4, +}; +static uint16_t group_MSA_EXT_5[] = { + S390_FEAT_GROUP_MSA_EXT_5, +}; + /* base features in order of release */ static uint16_t base_GEN7_GA1[] = { S390_FEAT_GROUP_PLO, @@ -435,6 +464,34 @@ static CpuFeatDefSpec CpuFeatDef[] = { CPU_FEAT_INITIALIZER(GEN13_GA2), }; +#define FEAT_GROUP_INITIALIZER(_name) \ + { \ + .name = "S390_FEAT_GROUP_LIST_" #_name, \ + .bits = \ + { .data = group_##_name, \ + .len = ARRAY_SIZE(group_##_name) }, \ + } + +typedef struct { + const char *name; + BitSpec bits; +} FeatGroupDefSpec; + +/******************************* + * feature groups + *******************************/ +static FeatGroupDefSpec FeatGroupDef[] = { + FEAT_GROUP_INITIALIZER(PLO), + FEAT_GROUP_INITIALIZER(TOD_CLOCK_STEERING), + FEAT_GROUP_INITIALIZER(GEN13_PTFF), + FEAT_GROUP_INITIALIZER(MSA), + FEAT_GROUP_INITIALIZER(MSA_EXT_1), + FEAT_GROUP_INITIALIZER(MSA_EXT_2), + FEAT_GROUP_INITIALIZER(MSA_EXT_3), + FEAT_GROUP_INITIALIZER(MSA_EXT_4), + FEAT_GROUP_INITIALIZER(MSA_EXT_5), +}; + static void set_bits(uint64_t list[], BitSpec bits) { uint32_t i; @@ -492,6 +549,28 @@ static void print_feature_defs(void) } } +static void print_feature_group_defs(void) +{ + int i, j; + + printf("\n/* CPU feature group list data */\n"); + + for (i = 0; i < ARRAY_SIZE(FeatGroupDef); i++) { + uint64_t feat[S390_FEAT_MAX / 64 + 1] = {}; + + set_bits(feat, FeatGroupDef[i].bits); + printf("#define %s\t", FeatGroupDef[i].name); + for (j = 0; j < ARRAY_SIZE(feat); j++) { + printf("0x%016"PRIx64"ULL", feat[j]); + if (j < ARRAY_SIZE(feat) - 1) { + printf(","); + } else { + printf("\n"); + } + } + } +} + int main(int argc, char *argv[]) { printf("/*\n" @@ -506,6 +585,7 @@ int main(int argc, char *argv[]) " */\n\n" "#ifndef %s\n#define %s\n", __FILE__, _YEARS, _NAME_H, _NAME_H); print_feature_defs(); + print_feature_group_defs(); printf("\n#endif\n"); return 0; }