From patchwork Mon Sep 5 20:40:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Paul X-Patchwork-Id: 9315255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC9C5607D3 for ; Mon, 5 Sep 2016 20:51:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 926312889A for ; Mon, 5 Sep 2016 20:51:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85CE8288AF; Mon, 5 Sep 2016 20:51:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C264D2889A for ; Mon, 5 Sep 2016 20:51:05 +0000 (UTC) Received: from localhost ([::1]:57026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh0r9-0005uA-KO for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Sep 2016 16:51:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh0hA-0004Pd-Ee for qemu-devel@nongnu.org; Mon, 05 Sep 2016 16:40:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh0h6-0004gx-9R for qemu-devel@nongnu.org; Mon, 05 Sep 2016 16:40:43 -0400 Received: from mail-pa0-x242.google.com ([2607:f8b0:400e:c03::242]:36800) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh0h5-0004gY-Mf for qemu-devel@nongnu.org; Mon, 05 Sep 2016 16:40:40 -0400 Received: by mail-pa0-x242.google.com with SMTP id ez1so9824102pab.3 for ; Mon, 05 Sep 2016 13:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=E6rRADxha/o9cY9wvmysEL/Pyxr4jz0mT2BNQv+f02I=; b=zUMxWfHIXt8/PxnfLRGuni+d64luLLk8/mnH5wtE34N3+xvL/pyeRHrsdWsz/8VlzF GUrAtfGs7Ilnin9wxp7TjrE5RYJlgVqX2jPb6aSUYxAbPnVPfwuWjcMwpi7Qu0tDhnnY VcaB97r2j6JsQLcYiZz3l2O191wqpSBeVgBDdvHE6BGC9Swd1kXz/fpJ3kVeUKglo/Y+ Xt7mMfjMV5MZKhc/hgD9eA5LJgc0q7UmSLobVQdGnx2qmU8fctoluf7t7ZuDK+NaJPs9 zJAMS+j591mZch5hC6fWmvS0SYWQa6S9HvbmQtL2IGiTehIChL4haEuEZRqMsFY0JVZF yUtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=E6rRADxha/o9cY9wvmysEL/Pyxr4jz0mT2BNQv+f02I=; b=NyzpK6pbc0mYCdRXTKvov/3eYRxHDI6wcgyuizLDRXXB1y9myIDVBtVQ6jEMZzJwkb JtvOJFyRd/eLAYtXX+w9VW9Xh4B7Wi3WBIsmEdgXhezbKXXfIUEndv2Bsfd98NSAYkvN m3bIia7oqvvrWQhy73ecq9MWpt0a8D1R25SMgA5bvHjL2NmyZd6tPzEx7Y4lXKopFtZ7 69KwNRE3qk39Czl5fsVrModuPBBUfnmuDG17aJEVt542rH2BB8EUkd8HPmiIMRGm6OSs e3m/0Vcsa1MNl1WRIalPjXoT1/F9bCRos4KiiZ8uGPok7zcwfOcLUqZCplPgw58fPNPL KLUA== X-Gm-Message-State: AE9vXwPJvNDjHscdLHpYLg0eTd6I+Pf/4Xx3dBRx1CfIeOBZi2LJ5ykwQ7twH+eN2rrgww== X-Received: by 10.66.9.42 with SMTP id w10mr66894918paa.34.1473108038653; Mon, 05 Sep 2016 13:40:38 -0700 (PDT) Received: from nuc.my.domain ([172.56.39.159]) by smtp.googlemail.com with ESMTPSA id hs7sm4364083pad.24.2016.09.05.13.40.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 13:40:38 -0700 (PDT) From: Bill Paul X-Google-Original-From: Bill Paul To: qemu-devel@nongnu.org Date: Mon, 5 Sep 2016 13:40:25 -0700 Message-Id: <20160905204025.30922-1-wpaul@windriver.com> X-Mailer: git-send-email 2.9.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c03::242 X-Mailman-Approved-At: Mon, 05 Sep 2016 16:50:28 -0400 Subject: [Qemu-devel] [PATCH] Fix TXE/TXEIE support in the STM32 USART model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This commit attempts to fix the behavior of the TX FIFO Empty bit in the STM32 USART driver. The two changes are: 1) After wrtiting to the data register, don't clear the TXE bit in the status register. The way this model works, the FIFO is effectively always empty. This is because we dump each character to qemu_chr_fe_write_all() right away and unlike real hardware we don't have to wait for the appropriate bits to be written to the I/O pins. 2) Implement support for the TXEIE (TXE interrupt enable) bit in CR1. When OS driver code unmasks this bit and TXE is set, this should trigger an interrupt to let the OS know the channel is now empty and it can send again. ChibiOS depends on the correct behavior of the TXE and the TXEIE interrupt. It checks to see if the TXE bit is set before trying to write any characters. however at the outset TXE is clear, so it blocks forever (or until you press a key at the serial console, which causes an RX interrupt that unjams in). Also once a character has been written, it waits for a TXEIE interrupt before sending the next character in a string. With these two fixes, it can now write to the serial port sucessfully. Signed-off-by: Bill Paul Cc: Paolo Bonzini --- hw/char/stm32f2xx_usart.c | 7 ++++++- include/hw/char/stm32f2xx_usart.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 15657ab..5671a7d 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -156,7 +156,6 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr, qemu_chr_fe_write_all(s->chr, &ch, 1); } s->usart_sr |= USART_SR_TC; - s->usart_sr &= ~USART_SR_TXE; } return; case USART_BRR: @@ -168,6 +167,12 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr, s->usart_sr & USART_SR_RXNE) { qemu_set_irq(s->irq, 1); } + + if (s->usart_cr1 & USART_CR1_TXEIE && + s->usart_sr & USART_SR_TXE) { + qemu_set_irq(s->irq, 1); + } + return; case USART_CR2: s->usart_cr2 = value; diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_usart.h index b97f192..2820209 100644 --- a/include/hw/char/stm32f2xx_usart.h +++ b/include/hw/char/stm32f2xx_usart.h @@ -44,6 +44,7 @@ #define USART_SR_RXNE (1 << 5) #define USART_CR1_UE (1 << 13) +#define USART_CR1_TXEIE (1 << 7) #define USART_CR1_RXNEIE (1 << 5) #define USART_CR1_TE (1 << 3) #define USART_CR1_RE (1 << 2)